AMD RyZen CPU Architecture for 2017

entity279 said:
So next - gen's picture may look even more promising for AMD (if they execute correctly, that is). Intel will certainly still use monolythic dies , and AMD will have likely improved upon a few low hanging fruits, architecture- and fabric- wise
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Well, i will not bet at 100% that Intel will keep the monolythic approach, or not completely. If not for the next CPU, the following. I will not even be surprised to see them release something in between ( maybe with only 2 "die" ( as a 2x 18 cores ) in some times, if not in some year. ( something who can recall their first quadcore ( who was 2x dualcore cpu die "glued" together )

Look even Nvidia have shown something who is going this way lately with their multi gpu die approach for exascale computers.. If absolutely not similar in design, we find the same spirit on it.
 
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Edit: over 3k cinebench for the 1950x at stock settings, impressive

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1920x (12c/24t): $799
1950x (16c/32t): $999
 
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The scaling is great on that 1950x, best run I've had on my 1700 with overclocked CPU + ram was around 1750.
 
There's absolutely no reason, Cinebench would not scale near ideally expect the CPUs throttles for power or thermal reasons. In CB r15, even Skylake-X is able to outshine Broadwell-E clock-for-clock.

FWIW, an "open" i9-7900X with a system power consumption of 285 watts clocks in at just above 2.200 in CBr15 (all-core 4 GHz).
 
Clukos said:
The scaling is great on that 1950x, best run I've had on my 1700 with overclocked CPU + ram was around 1750.
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Not bad for a bit of glue.

The voltage and thermals will be very interesting to see once they're released. At 180w one would think prosumers will simply throw an AIO on these things.
 
Malo said:
Not bad for a bit of glue.

The voltage and thermals will be very interesting to see once they're released. At 180w one would think prosumers will simply throw an AIO on these things.
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For what i have seen with Epyc, the TDP on paper is really higher than the real usage TDP (12 and 16cores with same rated TDP ( 3.5/4.0 vs 3.4/4.0 Ghz )... It will be interesting, due to the nature of "glued" dies if binning play a role in this regard.
 
Irregardless we now suddenly have access to high performance, high core count for much cheaper than yesterday. Not bad for a bit of glue.

The added PCIe slots are also most welcome.
 
Well i will wait full benchmark, but i m curious to see if we see some improvement even on other ryzen.. plateform should have a bit mature now.
 
How the language changes in time. When x86 chips integrated the northbridge with K8 and Nehalem, the ability to create a multisocket system without separate chips as the "glue" between CPUs was what made them capable of "glueless" SMP.
That still seems like an appropriate use of the glue terminology, and it can still have relevance when comparing multiprocessor systems.

It seems somewhat unfortunate to then try to use an application of glueless SMP as a marketing pejorative, although saying EPYC is four Ryzen dies "glueless-ied" together doesn't quite roll off the tongue. Surely there is some other adhesive or fastener metaphor they could use, like duct tape or a clamp.

It seems like AMD's next step might be to mitigate the fragmentation of the L3 and there not being a true large last-level cache in a later architecture. There are specific loads that having more L3 or maybe an L4 could absorb traffic or reduce the on-die component of the latency that contributes to the total cross-socket or intra MCM latency.

I'm curious how many of the IF links Threadripper has between the Zeppelin dies, or if there are architectural implications to having two chips communicating over more than one link.
 
The actual funny part will start when Intel releases their "glued" CPUs in the near future. And of course same true for Nvidia GPUs.

It will be interesting to see how the Glue evolves in its next iterations and see its true potential.
 
I think that, at a point, if you want to increase the number of cores, the simple question of using even 2x dies on an chip, instead of 2 independant CPUs, theres not much choice anyway. Is a 32 cores Epyc have slower on die communication versus 2x16 cores CPU on a 2P system ?

let alone the scalability production question.
 
Anarchist4000 said:
Isn't that how they attach the heat spreaders? o_O

I'd say the funny part already started.
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Well yes, but I was referring to their MCM products that surely will be the common thing in the industry.

Btw anyone have new info about IBMs light base communications? I was the new many years ago but it was never implemented. That would be a very very sticky glue.
 
Btw not to get too much into the Intel Meme but....If Intel a multi billion company which employee a good part of the best engineer can quote Wccftech, then it is acceptable for us to quote them also?
 
It's one that implies that naples will last 4 years without updating while Intel chips will update yearly.

Yes its almost false advertising but it doesn't say that directly its just show in a way that makes you(if ur stupid enough) think that.

Enviado desde mi HTC One mediante Tapatalk
 
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