AMD RDNA3 Specifications Discussion Thread

stupid question
at some point there was a rumor that amd will drop the HW scheduler for a software one
is that true? if so it maybe is at fault here?
 
stupid question
at some point there was a rumor that amd will drop the HW scheduler for a software one
is that true? if so it maybe is at fault here?
Should do the opposite of what we're seeing - make h/w simpler, reduce power consumption and allow it to clock higher.
There may be some negative effects on performance while the driver side compiler isn't tuned well for RDNA3 yet but it shouldn't be huge and it certainly shouldn't affect the clocks or anything.
 
How much utilization is 3.6 GHz Navi 31 getting in Blender? How well does Navi 21 clock in Blender vs games and how much utilization does it get in comparison?

ofc, you wouldn't expect a casual 60% overclock to be stable even with low utilization, but these are questions I'd like to see the answer to if only as a bit of a sanity check.
 
So it was all FUD. LOL
Maybe. They're not going to acknowledge it, regardless, unless they break something fundamental to the functioning of the thing.

"This is broken and we knew it before release" -> "This is an experimental feature not intended for this generation of product". (Though, the actual quote seems to outright deny that they broke something that was working in RDNA2.)

Unless we believe that they are slipping RDNA4 code into their public open source drivers before the release of RDNA3.
 
Maybe. They're not going to acknowledge it, regardless, unless they break something fundamental to the functioning of the thing.

"This is broken and we knew it before release" -> "This is an experimental feature not intended for this generation of product". (Though, the actual quote seems to outright deny that they broke something that was working in RDNA2.)

Unless we believe that they are slipping RDNA4 code into their public open source drivers before the release of RDNA3.
Bah!
Who has the press deck pdf?
 
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So it was all FUD. LOL

Anyone have the press release PDF of RDNA 3?
I do, what would you like from there?

Edit: and for reference, implementing features not actually used is standard practice, latest great examples being Intels DLVR in Rocket Lake and AMDs TSVs in Zen 3 since the beginning (or was it already in Zen 2, can't remember for sure)
 
I do, what would you like from there?

Edit: and for reference, implementing features not actually used is standard practice, latest great examples being Intels DLVR in Rocket Lake and AMDs TSVs in Zen 3 since the beginning (or was it already in Zen 2, can't remember for sure)
I was looking to read the entire PDF. Are you able to provide a link for it?
 
stupid question
at some point there was a rumor that amd will drop the HW scheduler for a software one
is that true? if so it maybe is at fault here?

RDNA1 & 2:
4.5. Manually Inserted Wait States (NOPs)
Inserting S_NOP is not required to achieve correct operation.

RDNA3:
5.6. Data Dependency Resolution
Inserting S_NOP is not required to achieve correct operation.
5.7. ALU Instruction Software Scheduling
...This instruction(S_DELAY_ALU) is optional - it is not necessary for correct operation.

I would say it's still hardware scheduler, with software hints to power off some parts of scheduler.
 
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Some good reads I found in the RDNA3 ISA document:
  • 4.1.1. Cache Controls: SLC, GLC and DLC
    • controls how load/store/atomic instructions interact with each cache level
  • 5.2. Instruction Clauses
    • talks about S_CLAUSE, followed by instructions on the same execution unit to be issued back-to-back without wave switching
  • 5.7. ALU Instruction Software Scheduling
    • talks about S_DELAY_ALU
  • 7.6. Dual Issue VALU
    • lists VOPD restrictions in detail
  • 7.9. Wave Matrix Multiply Accumulate (WMMA)
    • explains its matrix accelerator implementation
 
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