Might as well speculate this for Navi 31:
- 3x GCDs of 16x WGPs and 4096 VALU lanes, each about 100mm² +
- 3x MCDs of 128-bit GDDR and 128MB infinity cache, each around 150mm² +
- I/O die of 150mm²
- 24GB GDDR
That's 900mm² for 7900XT.
Then this for Navi 32, re-using Navi 31 chiplets:
- 2x GCDs of 16x WGPs and 4096 VALU lanes, each about 100mm² +
- 2x MCDs of 128-bit GDDR and 128MB infinity cache, each around 150mm² +
- I/O die of 150mm²
- 16GB GDDR
That's 650mm² for 7800XT.
Then Navi 33, 7700XT is approaching 400mm² as a monolithic GPU with 16x WGPs, 128MB infinity cache, 128-bit 8GB GDDR.
With the same chiplets used by both Navi 31 and 32, any broken WGPs would end up in the salvage SKUs:
- 7900 with 44 WGPs = 2x full GCDs + 1x GCD with 4x broken WGPs
- 7800 with 24 WGPs = 2x GCDs each with 4x broken WGPs
In the end, if AMD has learnt from Ryzen then small compute chiplets with lots of SKUs derived from partly-faulty premium chiplets seems likely. Zen 3 chiplets are 81mm², Zen 2 chiplets are 74mm², both on 7nm, relatively expensive in 2019 when Zen 2 launched.
You have to argue against this kind of SKU lineup built mostly from ~100mm² GCDs:
- 7900XT = 48 WGPs
- 7900 = 44 WGPs
- 7800XT = 32 WGPs
- 7800 = 24 WGPs
- 7700XT = 16 WGPs
- 7700 = ...
which maximises the return on 5nm wafers, when dismissing "multi-GCD" rumours.