AMD: RDNA 3 Speculation, Rumours and Discussion

[Bondrewd]

I noticed that Greymon's accuracy is slowly reducing
Looks like somebody clipped his sources

He's still the only Weibo tourist who filters his shit before posting so kudos to him I guess.

 

[Deleted member 90741]

He's still the only Weibo tourist who filters his shit before posting so kudos to him I guess.

But is there any truth to what he posts, then?

 

[Bondrewd]

But is there any truth to what he posts, then?

Some yes some no!
Filter it yourself based on what you know as usual.

 

[iroboto]

that's bs.

IIRC you mentioned that it will not be MCM?

 

[Bondrewd]

IIRC you mentioned that it will not be MCM?

That's N33.
He's BSing the TO date for N31.

 

[Leoneazzurro5]

That's N33.
He's BSing the TO date for N31.

So it has not yet taped out, or was it taped out earlier? Because some say that N33 will be the only RDNA3 part for 2022, while some say that also highend should come next year. But, if N31 taped out, the chance to see it in action next year rises a lot.

 

[iroboto]

So it has not yet taped out, or was it taped out earlier? Because some say that N33 will be the only RDNA3 part for 2022, while some say that also highend should come next year. But, if N31 taped out, the chance to see it in action next year rises a lot.

not too familiar with AMD naming conventions, but Is 33 the 'big chip' and the 31 the mainstream chip?

 

[Bondrewd]

but Is 33 the 'big chip' and the 31 the mainstream chip?

The opposite.
31 is the big chungus giga-MCP while 33 is the N6 mainstream single die.

 

[Tofu]

If 256bit N21 can have 32GB
https://videocardz.com/press-releas...o-v620-with-navi-21-gpu-and-32gb-gddr6-memory

why shouldn't N33 have 128bit and 16GB?

 

[Deleted member 13524]

If 256bit N21 can have 32GB
https://videocardz.com/press-releas...o-v620-with-navi-21-gpu-and-32gb-gddr6-memory

why shouldn't N33 have 128bit and 16GB?

It can and probably will use, even if GDDR6 densities of that time force it to use clamshell designs.

It doesn't look like N33 will be any cheaper than a 6800XT anyway...

 

[Bondrewd]

why shouldn't N33 have 128bit and 16GB?

Clamshells are very not practical in mainstream stuff.

It can and probably will use

Uhhhh ohhhhh.
#prayfor24GbitICs

 

[w0lfram]

I really think with the newer fabric AMD will achieved unified cache with dual/quad gpus. Raster is king for buying power and AMD knows this. As other suggest, AMD will dip into RT wholly, when gamers demand it...

 

[Bondrewd]

I really think with the newer fabric AMD will achieved unified cache with dual/quad gpus

It really is a single GPU with a somewhat funky topology.

As other suggest, AMD will dip into RT wholly, when gamers demand it...

Uhhhhh no only the biggest bars go!

 

[del42sa]

https://twitter.com/x/status/1457592130168184834

3D IF ? Cool

 

[Granath]

The IFC on Navi 31 GPUs will be split between two chips since it is an MCM design so it's still 256 MB per chip. The latest rumors now suggest that the Infinity Cache is also moving to a 3D stack design. So we aren't just getting MCM GPUs with RDNA 3 but there's also a possibility of getting stacking technology on the next-gen chips.

https://wccftech.com/amd-next-gen-rdna-gpus-feature-3d-infinity-cache-mcm-gpus-with-3d-stacking/

 

[no-X]

Is it really a new thing? Aren't the rumored active interposers / bridges (incorporating Infinity Cache) for Navi 21/22 already a 3D Infinity Cache solution?

 

[Bondrewd]

The IFC on Navi 31 GPUs will be split between two chips since it is an MCM design so it's still 256 MB per chip

Nope.

but there's also a possibility of getting stacking technology on the next-gen chips

Not a 'possibility' the thing is made like that.

Aren't the rumored active interposers / bridges (incorporating Infinity Cache) for Navi 21/22 already a 3D Infinity Cache solution?

bingo.

 

[yuri]

Correct me if I am wrong: The "bridge chip" bonding the two "computing chips" of Navi 3x together is glued on top of them. So the bridge itself actually is 3D. Since the bridging logic is not that big it doesn't seem probable to complicate the design by adding the 512MB cache as yet another 3D layer on top of the "bridge chip".

So yeah, it doesn't seem to bring any new info.

 

[Leoneazzurro5]

I think the idea is to bond (more than two) cache + I/O chips below the two compute dies in Navi31/32, not above. For the simple reason that you need to connect those I/O pins to the PCB.

 

[Jawed]

I think the idea is to bond (more than two) cache + I/O chips below the two compute dies in Navi31/32, not above. For the simple reason that you need to connect those I/O pins to the PCB.

Which I/O pins?