AMD: R8xx Speculation
- Thread starter Shtal
- Start date
That density is such a high priority for the ALU section probably is the reason for the relatively modest enhancements listed.
There is slightly better co-issue, slightly better precision for FP, an additional instruction, etc.
Then there is the reduced-precision integer math on the slim units that appears to be a step up from RV770, where only shifts were available.
This might mean that as time drags on that AMD might inch towards 32-bit integer operations across all units in the SIMD, as process nodes afford more space.
Not a lot to talk about there.
Cache and data-store wise, there are some bumps in capacity, so that merits half a second of discussion.
I guess we can hope Nvidia's next chip provides something more interesting than what has been leaked so far.
I'm still waiting on what has doubled the complexity of Evergreen's scheduler.
There is slightly better co-issue, slightly better precision for FP, an additional instruction, etc.
Then there is the reduced-precision integer math on the slim units that appears to be a step up from RV770, where only shifts were available.
This might mean that as time drags on that AMD might inch towards 32-bit integer operations across all units in the SIMD, as process nodes afford more space.
Not a lot to talk about there.
Cache and data-store wise, there are some bumps in capacity, so that merits half a second of discussion.
I guess we can hope Nvidia's next chip provides something more interesting than what has been leaked so far.
I'm still waiting on what has doubled the complexity of Evergreen's scheduler.
Silent_Buddha
Legend
I've been reading every page of this thread and noone has said AMD has been profitable. Not sure where you got that. Slappi certainly wasn't responding to it.
What may have been implied is that the ATI (graphics) division within AMD has been more profitable than Nvidia, and that's at least true for the last quarter, although both lost money.
I'm pretty sure everyone here will quite happily admit that AMD has been losing money for quite a while now.
Regards,
SB
AMD IS losing money and WILL lose money in the foreseeable future.
Perhaps you need to read a bit more carefully. Not sure why you're mentioning AMD, this statement of Neliz was about ATI.
okay, go over to the AMD Doom&Gloom thread and quote this from me, please:
neliz said:
More speculation please, Will the packages contain dongles or not?
Silent_Buddha
Legend
I would assume you bringing in AMD financials would have something to do with that. Since NVDA financials were brought up to counter the claim that NVDA has been profitable this past year.
Regards,
SB
This:
That's not true. Simple. nVidia is making loss. I can't get, why do you have a problem when I corrected evidently wrong information.
NVDA financials were brought in to demonstrate ATI's loss was relatively small. In turn, AMD financials demonstrate that NVDA's loss was relatively small. It works both ways.
We finally get some probable design information, and we waste pages on the public knowledge that AMD and Nvidia lose money, a fact that has been beaten over on two doom/strain threads where such facts are on-topic.
Here's an on-topic idea for this thread.
The SIMD array is apparently banked, with two separate arrays.
The ROP groups do not appear to be similarly divided.
Is this just a diagram simplification, or is there something more to this?
Here's an on-topic idea for this thread.
The SIMD array is apparently banked, with two separate arrays.
The ROP groups do not appear to be similarly divided.
Is this just a diagram simplification, or is there something more to this?
Are the double ROPS a resultant of, for instance double-Z or are requirement bceause of it?
Jawed
Legend
Yeah, looks problematic to me. Can't think of any justification other than "scaling bandwidth to 20 clusters is extremely hard".
Is prunedtree's matrix multiplication L2->L1 bandwidth-limited?
Interesting, all the same, that ALU:TEX remains at 4:1. The L2->L1 bandwidth limitation might make it, in effect, 8:1 though.
The dual rasterisers etc. is some kind of big deal. I presume Hierarchical-Z/stencil is partitioned into two and this is done with a simple tiling in screen space.
There's no interpolator unit. I wonder if this has something to do with tessellation being an interpolator of sorts. The D3D11 tessellator generates interpolated vertex coordinates based on existing vertices and tessellation factors.
Jawed
There are two rasterizer blocks, two SIMD banks, and then there is the ROP section.
The L shaped purple blocks on the side of each ROP block apparently have links to both hierarchical Z blocks.
This would seem to indicate that even though the earlier parts of the process are split, the ROPs have a unified view, possibly for the sake of correctness if two rasterizers have outputs that will lead to gibberish if they write out without some kind of order being put in place.
If all 32 ROPs do work in concert, it would be the case that a single 16-lane SIMD would not be capable of outputing enough per cycle to go to all 32 ROPs.
Maybe the ROPs are more flexible in allocation than the diagram indicates, there is some kind of buffering stage such that a SIMD's output over two or more cycles is built up before sending to a ROP, or somehow there is a way to send more than one SIMD-worth of output to the ROPs.
If the ROPs still work as a unit, maybe it could be that one SIMD bank might be running a fill-rate limited set of code, while the other could be running some ALU or texture-limited work, and the ROPs could concentrate on one side of the chip over the other.
Interpolation was moved inside the shader cores.
Yep, that seems to be the case. Fragments reordering is probably done there therefore it needs to be coherent with the rest. Moreover they need to be able to send back z-related info to the Hi-Z blocks so that they can update their low res conservative z-buffer representations.
Jawed
Legend
Seems it can only be 256-bit.
The performance appears to be ~50% higher than HD4890. Sure it's better than the seeming bandwidth increase, but RV770 seemed to have quite a bit of excess bandwidth particularly for 4xMSAA.
As to the architecture, well it's certainly food for thought. Too early to tell how radical they've been, because for example the append/consume buffers could be one linchpin of radical efficiency gains - but how to tell?
It's kinda interesting that this has 80 TUs and 32 RBEs, basically the same numbers as GT200 (except Z rate, of course). Slight difference in GFLOPs
, very similar bandwidth I guess and some storming comparative performance. But I expected more I'm afraid.Maybe the reviews will change my mind. HD4890 was seriously underwhelming and the performance gain of HD5870 seems to be merely adequate over 15 months. Maybe there's some compute-heavy games around the corner and the beast is otherwise dormant.
The STALKER Clear Sky performance numbers are badly disappointing, STALKER (versions and mods) is one game I've been delaying playing until there's a card that can own it.
Jawed
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