AMD: R8xx Speculation

How soon will Nvidia respond with GT300 to upcoming ATI-RV870 lineup GPUs

  • Within 1 or 2 weeks

    Votes: 1 0.6%
  • Within a month

    Votes: 5 3.2%
  • Within couple months

    Votes: 28 18.1%
  • Very late this year

    Votes: 52 33.5%
  • Not until next year

    Votes: 69 44.5%

  • Total voters
    155
  • Poll closed .
neliz, you can ask charlie for below leaking info, I don't translate them

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I don't mind the name "Radeon 7 Series", it's the dumb "7" in the fake logo that was posted that I didn't like.

Well that and all the tree names. Is it supposed to be a whole "going green" thing? I just don't get it. Were the marketing guys sitting around brainstorming about what best represents the new mighty awesome gaming power and excitement of their new line-up, and they came up with TREES?

I don't get it. :(
 
Even without tessellation this is a basic problem. The same pixel might appear on several triangles that are in flight at the same time. I honestly don't know how developers are going to make much use of pixel read/write when the render target is constantly changing.

That is exactly the point I was attempting to make!

I don't understand what it is about the tessellation case that creates a problem here. Tessellation is followed by setup then rasterisation. Tessellation is transparent as far as a fragment is concerned.

Right, I wasn't implying that tessellation creates a new problem. It will likely be more frequent however...
 
From XS forums (link):

Radeon "7" Family (Evergreen) is 6 parts:
Trillian = "R800" + either multiple montior or 3-way GPU
Hemlock = "R800" Dual GPU
Cypress = "RV870" Single GPU
Juniper = "RV840"
Redwood = "RV830"
Cedar = "RV810"
Press date: Sept 10th, 2009 Event loc. San Fran, USA?
Hard release: Sept 24th. --> mid Nov. 2009
Price range: $500 (high-end) --> $50 (low-end Cedar)

Cypress (rv870) single gpu "HD5870" is:
HD2900XT PCB size
40nm
353mm^2 die size
19mm x 19mm at cost of $34 per die
2x 6pin PCI_E power connectors
DX11
1600SP
256bit bus
80TMU
32ROP
1024/2048mb mem configs
SIMD : 20
Shader Clock : 850 ???
Memory Clock : 1200 ???
Bandwidth : 153Gbps ???
~$350 MSRP
3dmark vantage performance:
Cypress ~P16xxx - P17xxx - P18xxx
aka ~HD4870X2 performance level
potentially an ~30% performance improvement in the same power profile vs. rv770

Hemlock (R800) dual gpu "HD5870x2" is:
larger than 4870x2 single PCB
40nm 353mm^2 die x 2
19mm x 19mm at cost of $34 per die
1 6pin + 1 8pin PCI_E power connectors
DX11
3200SP
256bit bus x 2
80TMU x 2
32ROP x 2
1024/2048mb x 2 mem configs ???
~$500 MSRP
3dmark vantage performance:
(2x Cypress) theoretical P34xxx ???

Juniper/Redwood HD5850, HD5830, HD5770?
Partial shroud HSF design
40nm
181mm^2 die size
14mm x 14mm die
1 6pin PCI_E power connector
DX11
800SP on Redwood
640SP on Juniper
128bit bus
40TMU
16ROP
512/1024mb mem configs???
~$199/$149 MSRP
3dmark vantage performance:
Juniper XT ~P95xx
Redwood ~P46xx
About the speed of a HD4870 & HD3870
 
The LDS "exchange" mechanism is atomic (i.e. write/read are indivisible), because a clause encapsulates the LDS instructions. But ATI cannot currently support an atomic: "import data into registers, execute ALU cycles, export data from registers" because that's 3 clauses - ALU instructions cannot operate on non-register memory, except for fetching from constant buffers.

BTW, thanks for the ATI details!
 
From XS forums (link):

I'm 99% sure that they're wrong - not necessarily spec-wise, but naming wise - as in, I'm quite positive on "HD5870" and "HD5850", or whatever the names will be, share the same chip

Not to mention that first calling it "Radeon 7 series" and then the old names doesn't sound right at all, I mean would we be buying "Radeon 7 HD 5870"'s next?
 
I'm 99% sure that they're wrong - not necessarily spec-wise, but naming wise - as in, I'm quite positive on "HD5870" and "HD5850", or whatever the names will be, share the same chip

Not to mention that first calling it "Radeon 7 series" and then the old names doesn't sound right at all, I mean would we be buying "Radeon 7 HD 5870"'s next?

That post just sums up everything WE discussed and Charlie printed in the last four weeks.

B....S....

(and they still didn't put all the things together properly)
 
Plenty more like that in http://developer.amd.com/gpu_assets/R700-Family_Instruction_Set_Architecture.pdf

Which reminds me:

http://forum.beyond3d.com/showpost.php?p=1292190&postcount=613

Code:
srv_struct_load   srv_raw_load      dcl_struct_srv    dcl_raw_srv      append_buf_consume      append_buf_alloc
There's also atomics for UAV:
Code:
uav_read_cmp_xchg uav_read_xchg     uav_read_xor      uav_read_or      uav_read_and      uav_read_umax     uav_read_umin     uav_read_max      uav_read_min      uav_read_rsub     uav_read_sub      uav_read_add      uav_cmp     uav_xor     uav_or      uav_and     uav_umax    uav_umin      uav_max     uav_min     uav_rsub    uav_sub     uav_add      uav_struct_store  uav_raw_store     uav_store   uav_struct_load      uav_raw_load      uav_load
and atomics for LDS:
Code:
lds_read_cmp_xchg lds_read_xchg     lds_read_xor      lds_read_or      lds_read_and      lds_read_umax     lds_read_umin     lds_read_max      lds_read_min      lds_read_rsub     lds_read_sub      lds_read_add      lds_cmp     lds_xor     lds_or      lds_and     lds_umax    lds_umin      lds_max     lds_min     lds_rsub    lds_sub     lds_add      lds_store_vec     lds_load_vec      lds_store   lds_load

Jawed
 
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