AMD: R8xx Speculation

Hmm, there's a 181 mm chip (which I assume is juniper) and Cypress (according 2 charlie) is 19 mm a side (btw, 19x19=361 and 181*2 = 362). Then that suggests that an cypress is an MCM. And if Juniper is an 640 alu chip, then Cypress is an 1280 alu chip, as has been rumored before.

( For MCMs, side doesn't make much sense, but I think he did this just to compare how much would a chip cost. )

IMHO, a MCM is the only way they can justify a $300 part at 360mm2. Otherwise, this is a sour spot. And we are seeing the mid range chips blow up in size similar to the way high end chips blew up from R300 to GT200. Die sizes have gone from 192 mm->260->360 mm, almost double in a matter of 2 years.

And the packaging trouble rumours dont fit any where at all if it is not a MCM. Why would they have a problem packing a 360 mm2 monolithic die?

Of course all of this is after taking charlie at face value.

 

Just to belatedly apologize, sorry for making posts and then not responding to add to the conversation, I haven't had the time to keep up on these things as much as I used to.

Nordic (Andreas) posted that he has more or less confirmed the 384-bit bus.

While I may have been one of the larger proponents of this gen being MCM, I really don't have any clue anymore...(mis)information coming from too many angles to keep up with, and I'll be daamitted if I'm not confused by the abundance of codenames.

All I can speculate to is that I bet the high-end part uses DDR5@ 4800mhz...Doubling the bandwidth from Rv770.

 

If the odd size buses are true... then the ROP count would be different from what he is reporting...

 

He says 384 Bit for the X2, though, doesn't he?

 

Which is quite odd indeed.
I'd sooner believe in 384 for RV870, 768 for X2 config.
Or even (if we're crazy enough to talk this MCM bullshit further) something like 256->384->512 with more and more memory channels allocated for chip-to-chip communication.

 

But what's an X2? (Yeah, that's right...I brought the MCM bullshit further)

I think that is speculation, although I'm not sure.

I seem to remember Napoleon over @ Chiphell saying a while back the chip was planned as 960/48/192-bit when news started breaking as an 800/40/128-bit chip, although that isn't necessarily correct.

Still, when he said it, it seemed like he was letting it out because he had resigned to the fact it had changed because of shitty yields.

 

There's too much fud flying around to believe any of it....

 

I agree, it's silly season alright. Didn't we discuss the possibility of a 192-bit bus based on the die size earlier though? I'll admit it feels very compelling to me. 2x384-bit with a massively TDP-optimized bin would also be one hell of a monster, although I don't think there's anything to back up that speculation right now.

 

Is a 384 bit memory interface under 300 sqmm possible? I am skeptical.

 

/me runs into the thread wearing a gold sparkling jacket and blowing a party horn whilst tossing confetti in the air from a bucket

 

Can we take pictures for your children?

 

Prolly not quite, once you account for the other interfaces. I reckon ~56mm perimeter for GDDR5 and 19mm for the other interfaces - though they're open to a fair bit of tweaking, I expect, perhaps to the extent of making them take only 10mm of perimeter.

Jawed

 

I don't understand, I thought we were talking ~350-360 (either as a single die per Chollie or 192-bit mcm of the 180mm part), which really falls right in line with nvidia's ability to make the ~470mm2 GT200b 512-bit, almost exactly. Granted, I'm a layman not knowing how much space is needed for a GDDR5 controller over one that's GDDR3, but I'm still surprised to this day ATi fit a 256-bit bus on rv670. Heck, even the 420mm(ish?) R600 had a 512-bit controller, which would imply that at least that generations controller could achieve 384-bit with a die around 320mm2. Is it so absurd a chip slightly smaller than rv670 and needing GDDR5 compatibility would sacrifice this odd slice of bus bandwidth, or be enhanced over say one that's 128-bit? Is the bus tied into any part of the architecture that would make this unfeasible? I don't see how die size would be the problem. My apologies if this was discussed and I didn't catch it. When I get a chance to soak in ya'lls knowledge, it's usually just the last couple pages of the thread.

Haha. Did you just get the random inclination, or did something show up on your desk as well?

 

So 24 days to go.......


waiting eagerly

 

So where is the source of this news?
Is it Asia or this thread?

 

September 10th, no one would have thought that

 

here is the source:

http://techpulse360.com/2009/08/12/...en-graphics-chips-you-wont-believe-your-eyes/

(yes, it's been up for a couple of days!)

 

this's the real source: 发表于 2009-8-12 16:55 (GMT+8), which else is earlier than this ?

http://bbs.pczilla.net/thread-3685-1-1.html

 

Nah, this is the real source: