AMD: R8xx Speculation
- Thread starter Shtal
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Way too slow and probably a whole bunch of electrical and mechanical problems due to the high temperatures. (And if you want to do it faster, you'd have to increase laser power, which would make it worse.)
Also, in the current system, you first tape the wafer to a plastic layer and control the saw just so that it cuts through the wafer, but not through the plastic, so everything stays nicely in place. Can't do that with a laser...
I'm not saying it's impossible, but remember, you want to do this to save costs, so you want everything as standard as can be.
Why not just kill the non-functioning cores off in the BIOS? Sure enthusiasts would figure out how to enable them, but they'd be taking their chances on the yields and I personally still think that kind of thing adds to sales. 
TSMC CEO claims improved 40nm yield, predicts better 3Q09
http://www.digitimes.com/news/a20090731PD204.html
http://www.digitimes.com/news/a20090731PD204.html
Cutting the wafer with a laser (or perhaps just the selective cuts) may not be as expensive or difficult as it might seem initially. Below are some examples of wafer cutting using lasers:
http://www.coherent.com/Applications/index.cfm?fuseaction=forms.AppLevel2&AppLevel2ID=59
http://www.synova.ch/pdf/2000_Korea_Swit.pdf
The first link mentions:
"Silicon wafer cut speeds achieved using the AVIA-X q-switched DPSS laser are comparable with mechanical methods, and offer the benefits of reduced chipping and simplified handling requirements as compared to mechanical techniques."
In the second link they mention:
"The diamond saw-blade exerts extremely high forces on the
wafer during the sawing process, which make it necessary to
fix the wafer firmly in place and can lead to parts becoming
chipped at the edges and corners and cracks occurring in the
wafer, which can subsequently lead to circuit failure.
The most significant problem of abrasive sawing is the
chipping at the upper and lower edges of the cut – chipping
across the width of the line and into the die will inevitably
lead to rejection. Laser processing on the other hand, being
virtually force-free, means that chipping is not a problem."
"The running costs of the saw are very high on account of the
consumption of diamond-edged saw-blades. Furthermore, the
manufacturing process has to be stopped for a tool change, and
the actual change performed manually. Although somewhat
more expensive to purchase, the laser is characterised by
extremely low running costs. The laser flashlamps have to be
replaced after approx. 800 to 1000 hours, and the diamond
waterjet nozzles after approx. 200 hours. All in all, this
equates to considerably lower consumption costs for the laser."
As far as disabling cores in the bios. It works of course. However, it means packaging some lower core chips in larger packages which would increase the number of SKUs for the same chip, since you would still want to create chips with fewer cores directly (since these chips are usually the higher volume ones).
In either case, I think putting multiple dice on the same piece of silicon as a means of scaling across a range of performance GPUs with a single design might make a lot of sense.
http://www.coherent.com/Applications/index.cfm?fuseaction=forms.AppLevel2&AppLevel2ID=59
http://www.synova.ch/pdf/2000_Korea_Swit.pdf
The first link mentions:
"Silicon wafer cut speeds achieved using the AVIA-X q-switched DPSS laser are comparable with mechanical methods, and offer the benefits of reduced chipping and simplified handling requirements as compared to mechanical techniques."
In the second link they mention:
"The diamond saw-blade exerts extremely high forces on the
wafer during the sawing process, which make it necessary to
fix the wafer firmly in place and can lead to parts becoming
chipped at the edges and corners and cracks occurring in the
wafer, which can subsequently lead to circuit failure.
The most significant problem of abrasive sawing is the
chipping at the upper and lower edges of the cut – chipping
across the width of the line and into the die will inevitably
lead to rejection. Laser processing on the other hand, being
virtually force-free, means that chipping is not a problem."
"The running costs of the saw are very high on account of the
consumption of diamond-edged saw-blades. Furthermore, the
manufacturing process has to be stopped for a tool change, and
the actual change performed manually. Although somewhat
more expensive to purchase, the laser is characterised by
extremely low running costs. The laser flashlamps have to be
replaced after approx. 800 to 1000 hours, and the diamond
waterjet nozzles after approx. 200 hours. All in all, this
equates to considerably lower consumption costs for the laser."
As far as disabling cores in the bios. It works of course. However, it means packaging some lower core chips in larger packages which would increase the number of SKUs for the same chip, since you would still want to create chips with fewer cores directly (since these chips are usually the higher volume ones).
In either case, I think putting multiple dice on the same piece of silicon as a means of scaling across a range of performance GPUs with a single design might make a lot of sense.
According to intel's slidedeck "how a cpu is made" they still uses Saw instead of LASER.
Now that I think of it, you're right, I just remember reading something about laser cutting parts of the chip to disable them, but guess it was either misinformation or that the laser is just used to "blow the fuses"
Probably.
But back to Intel - how could they tell when to cut single and dual cores? And I believe they did not just randomly pick some pairs from the middle of the wafer, because they later sold Smitfields ridiculously cheap (althought those were slower variants and the manufacturing tech was very mature by then, so who knows...)
But back to Intel - how could they tell when to cut single and dual cores? And I believe they did not just randomly pick some pairs from the middle of the wafer, because they later sold Smitfields ridiculously cheap (althought those were slower variants and the manufacturing tech was very mature by then, so who knows...)
It's hot, but not particularly so in the remaining material ... that's the beauty of flash ablation, gas doesn't conduct heat very well. As for speeding it up, there is always parallelism.
GPU work is already massively parallel. Any partition injects at least a minimal amount of restriction in how parallel the GPU solution can work, on the other side of the equation, physical implementations can't scale without bound and many of the things we implement in hardware expand in complexity faster than the benefits they provide.
There's going to be a trade-off no matter what decision is made.
There is a reticle limit that imposes a ceiling on the dimensions a single exposed die can have.
However, there are large chips that exceed the size that can be physically made. I believe large CMOS sensors are an example, where there are many sensor dies that are "stitched" together at a higher level of interconnect.
This has been talked about before.
http://forum.beyond3d.com/showthread.php?t=45110
Intel's Smithfield was a dual-core solution where Intel basically neglected to saw apart two dies.
They were wired together at the package level.
There may have been some incremental improvement in some of the electrical behavior over just having two sockets, but this was mostly a quick and dirty way to beat AMD's "native" dual core approach by a pretty good margin.
(edit: for clarity, beat to market)
For a volume product at volume prices, irregular cutting and re-sawing dies when one core tests badly didn't happen.
Pairs of cores were cut out ahead of knowing which ones would work out. It would have been cheaper to throw bad ones out than to waste time and money on trying to pick good pairs out.
Some testing is done before the die is put onto a package substrate, which might find some early faults. It would still be too late to cut the chip in half as it's an awfuly fiddly job to then take a tiny die back to be sawed in half.
Things need to be tested after the chip is on a package, and by then it's now soldered and affixed to something that cannot be cut, and now it's too late.
I suppose it could be possible to turn one core off and sell the double-dice as a single-core. I don't know if Intel did this or just tossed them.
Yields should have been already good for single cores, so it would be hoped the dual-core solution would take an acceptable yield hit for the price premium.
Intra-wafer variation usually wasn't too bad for neighboring cores, though power is pretty much doubled.
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BSN -> bullshit news?
Both BSN and Hardware-Infos were adament that we would have all the D12U info we needed around May/Computex.
I'm still checking the sites and waiting for it... Daily.
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