AMD: R8xx Speculation

[Kaotik]

I thought we were expecting a small bump in SPs compared to RV770/790 for the RV830?

Heck, do even know the wafer shown was "RV830" and not "RV870"?
No, we don't, all we know is we've seen ~180mm^2 chip, which would probably be able to fit more SPs than RV770 has, depending on additional space needed by DX11 support - and again, this is assuming it's even based on the same basic design and not "completely from a scratch"

 

[swaaye]

Where's my 32 pipe R520!? Or was that a rumor for R420?! Can't remember now...

 

[LordEC911]

Heck, do even know the wafer shown was "RV830" and not "RV870"?
No, we don't, all we know is we've seen ~180mm^2 chip, which would probably be able to fit more SPs than RV770 has, depending on additional space needed by DX11 support - and again, this is assuming it's even based on the same basic design and not "completely from a scratch"

True, I agree there is too much unknown but I really doubt that a 180mm2 is going to be their next performance chip. 128bit-192bit bus would be easy, a 256bit bus would be cutting it pretty close. I guess I am expecting their new performance chip to have a 256bit bus and am questioning if this 180mm2 chip can fit it.

I also am assuming that RV8xx is just a tweaked R600/R700, I would imagine that we would have heard about a new architecture before now and it does seem to be working pretty well for them, with some making it sound like DX11 isn't too big of a jump for them, i.e. not needing a huge architecture tweak.

 

[Ailuros]

I also am assuming that RV8xx is just a tweaked R600/R700, I would imagine that we would have heard about a new architecture before now and it does seem to be working pretty well for them, with some making it sound like DX11 isn't too big of a jump for them, i.e. not needing a huge architecture tweak.

D3D11 isn't equivalent in the amount of changes it brings with it to D3D10.1 vs. D3D10. Usually a new technology generation brings some significant architectural changes with it and no X11 is not all about some pre-existing part of the final required tessellation package of the API.

In any case any coming X11 GPU will have in its majority compliance for the requirements of the API and IHVs can worry about real X11 performance years later than 2009. However if you're offering say just 30-40% more performance with a X11 GPU compared to it's predecessor do you think it's a bigger selling point than having a damn fast or even the fastest "DX10" GPU with the X11 sticker on the box?


I'm still wondering why the hypothetical specs speak of 32 pixels/clocks or else 32 ROPs if you prefer. One good reason that would pop into my mind is that the efficiency in the rasterizing/tri setup part could have increased by a healthy portion. And that would be one detail enough to not think of it as a "RV770 with X11 compliance slapped on", but one "detail" that could deliver far higher performance than more than currently expected SPs. Don't ask me how they'll do I'm tapping in the dark here as anyone else.

There's a lot of low hanging fruit for further efficiency increases for both IHVs and developers have repeatedly mentioned that future GPUs might or should increase in the rasterizing department.

Besides what do you expect to hear before the official launch anyway? Take the other side of the riverbank; rumored to have 512SPs. Is that good enough to assume that it's also just a "GT200+X11" ?

Anyway my only other spot that somewhat worries me is that the hypothetical specs point in the smallest increase being raw memory bandwidth. But as I always say over the years it's not the bandwidth amount that matters but rather how you handle it. It could very well be that say 140+GB/s are enough for such a chip.

Or the entire story is wrong and we're facing another 480 vs. 800SP fiasco as with RV770

 

[trinibwoy]

Because branch granularity isn't the most important thing?

Sure but why move backwards when obviously future applications are going to make more use of dynamic branching, not less? ATI went from 16-48-64, it's doubtful they're going to further increase batch size.

Or the entire story is wrong and we're facing another 480 vs. 800SP fiasco as with RV770

My money is on that.

 

[Mintmaster]

I'm still wondering why the hypothetical specs speak of 32 pixels/clocks or else 32 ROPs if you prefer. One good reason that would pop into my mind is that the efficiency in the rasterizing/tri setup part could have increased by a healthy portion. And that would be one detail enough to not think of it as a "RV770 with X11 compliance slapped on", but one "detail" that could deliver far higher performance than more than currently expected SPs. Don't ask me how they'll do I'm tapping in the dark here as anyone else.

Remember that RV740 has 16 ROPs on a 128-bit bus, so this doesn't necessarily mean anything. With the BW of GDDR5, it makes sense to double the ROPs per memory channel. It's still an important part of performance, especially with alpha tested polygons in jungle scenes.

Still, I agree that multiple tris per clk setup would be awesome, and I really hope you're right.

 

[Jawed]

Does tessellation warrant a higher setup rate?

More triangles per frame or more correctly-sized triangles per frame?

Jawed

 

[Ailuros]

Remember that RV740 has 16 ROPs on a 128-bit bus, so this doesn't necessarily mean anything. With the BW of GDDR5, it makes sense to double the ROPs per memory channel. It's still an important part of performance, especially with alpha tested polygons in jungle scenes.

Of course does it make sense but then again the RV740 is a mainstream part and has a totally different target market. No IHV will promise at the street price of those fluent performance in high resolutions.

The question would be if it makes a difference how much theoretical raw bandwidth is available per ROP. Speculative math:

RV770 = 115200 / 16 = 7.2 GB/s per ROP
"RV870" = 140800 / 32 = 4.4 GB/s per ROP

The ratio could be worse if one would compare the bandwidth to pixel fillrate relation.

Still, I agree that multiple tris per clk setup would be awesome, and I really hope you're right.

I'd very surprised if you wouldn't agree

Does tessellation warrant a higher setup rate?

More triangles per frame or more correctly-sized triangles per frame?

Good questions; I can't obviously answer any of the two as a layman but I'd rather ask how any of the two IHVs plan to handle general efficiency with a lot of small triangles. It might not warrant an immediate answer from IHVs but in the longrun when tesselation appears in the distant future in games it might be a headache for them. Even more so when it comes to multisampling and no I don't think NV's coalescing patent could be an adequate solution for that one either.

 

[KonKort]

AMD RV870 assumingly coming in October

http://www.hardware-infos.com/news.php?news=3038&sprache=1

 

[Arty]

AMD RV870 assumingly coming in October

http://www.hardware-infos.com/news.php?news=3038&sprache=1

Yes "SA" beat you to it, I remember you latched onto CJ's "RV870 is coming earlier than expected, many will be surprised" as an August launch.

 

[Tchock]

Something going on in Chinese Chiphell again.


1. GT300 big, so yields predictably unreasonable as of now (meh)
2. RV870 takes 10+ USD in terms of "testing fees", packaging/testing dept. isn't too keen on accepting the order list due to "complexity". Hmm?
3. RV830 is smooth sailing.
4. nVidia and GloFo hanky panky.

Mainly 2 is the object of interest. I haven't heard of packaging complexities before, maybe it's underrated wrt the ever ongoing discussion of diesize and yields?

Or maybe... the 180mm^2 chip is RV830, and doing an MCM of 2 Shanghai sized GPUs with a proper interconnect is quite a daunting task.

Anyone?

 

[Ailuros]

1,3 & 4 I'd say probably yes. 2 sounds way too weird but you never know.

What's a RV830X2 supposed to bring anyway? Something about hypothetical 4890X2 performance with a DX11 sticker slapped on?

If something like the RV830 is going to arrive first (let's say ~Q3) AMD could land a shitload of mobile OEM deals with it.

 

[Arty]

Where's my 32 pipe R520!? Or was that a rumor for R420?! Can't remember now...

Extreme pipelines now extreme SIMDs.

 

[Ailuros]

How bout EverSPees?

 

[Jawed]

Mainly 2 is the object of interest. I haven't heard of packaging complexities before, maybe it's underrated wrt the ever ongoing discussion of diesize and yields?

Or maybe... the 180mm^2 chip is RV830, and doing an MCM of 2 Shanghai sized GPUs with a proper interconnect is quite a daunting task.

E4690 is an MCM of GPU + 4x GDDR3. What's the packaging cost and testing complexity?

Maybe it's die-stacking?

Die Stacking for Desktop GPUs?

Jawed

 

[KonKort]

Yes "SA" beat you to it, I remember you latched onto CJ's "RV870 is coming earlier than expected, many will be surprised" as an August launch.

No, I get the informations from other sources. But of course I am in contact with Charlie, too.
Well, there were much trouble about RV870 launch. In the spring I get the info that RV870 can launch in this summer. Then grow TSMCs problems and RV870 was set to September. Now it looks like he really comes in October.

 

[Vincent]

D3D11 isn't equivalent in the amount of changes it brings with it to D3D10.1 vs. D3D10. Usually a new technology generation brings some significant architectural changes with it and no X11 is not all about some pre-existing part of the final required tessellation package of the API.

In any case any coming X11 GPU will have in its majority compliance for the requirements of the API and IHVs can worry about real X11 performance years later than 2009. However if you're offering say just 30-40% more performance with a X11 GPU compared to it's predecessor do you think it's a bigger selling point than having a damn fast or even the fastest "DX10" GPU with the X11 sticker on the box?


I'm still wondering why the hypothetical specs speak of 32 pixels/clocks or else 32 ROPs if you prefer. One good reason that would pop into my mind is that the efficiency in the rasterizing/tri setup part could have increased by a healthy portion. And that would be one detail enough to not think of it as a "RV770 with X11 compliance slapped on", but one "detail" that could deliver far higher performance than more than currently expected SPs. Don't ask me how they'll do I'm tapping in the dark here as anyone else.

There's a lot of low hanging fruit for further efficiency increases for both IHVs and developers have repeatedly mentioned that future GPUs might or should increase in the rasterizing department.

Besides what do you expect to hear before the official launch anyway? Take the other side of the riverbank; rumored to have 512SPs. Is that good enough to assume that it's also just a "GT200+X11" ?

Anyway my only other spot that somewhat worries me is that the hypothetical specs point in the smallest increase being raw memory bandwidth. But as I always say over the years it's not the bandwidth amount that matters but rather how you handle it. It could very well be that say 140+GB/s are enough for such a chip.

Or the entire story is wrong and we're facing another 480 vs. 800SP fiasco as with RV770

I am betting this time that RV870XT will be on par with GTS 360 in terms of cost/performance.

 

[Kaotik]

I am betting this time that RV870XT will be on par with GTS 360 in terms of cost/performance.

So it would be worse than RV770XT compared to GT200's GTX260 variant? (beating in both price and performance until 216-core version)

 

[trinibwoy]

I am betting this time that RV870XT will be on par with GTS 360 in terms of cost/performance.

Isn't that what happened last time?

 

[aaronspink]

E4690 is an MCM of GPU + 4x GDDR3. What's the packaging cost and testing complexity?

Putting some bog standard DDR packaged chips onto a package substrate is a bit of a joke really. The tolerances and pad areas are incredibly large. It is about as hard as putting them on any normal PCB really.

Test flow is also fairly simple, put on GPU die, run in test bench, if passes, add DRAM.

On the other hand, putting two actual dies down with tight pitch landing pads and testing is another whole matter entirely. 2x the tester throughput is required vs 1 die. A lot more failed product, etc. Lots more work and risk.