AMD: R7xx Speculation

[LordEC911]

Maybe they got rid of something?

Tesselation? UVD2 shaved some unnecessary fat?
Not much else other than that.

 

[trinibwoy]

But that goes against the TFlop target.

Yeah I noticed that all speculation thus far has been based on an assumption of 1 teraflop.

Maybe they got rid of something?

The unused tesselation unit would be one candidate.

 

[Wirmish]

What I thought...

6 x 80-SPU blocks -> 6 x 16 x 5D -> 96 x 5D (Dave Orton, october 6, 2006)
6 Texture Units x 4 Texture Filter Unit -> 24 "TMUs" (Maybe 8 TFU per TU -> 48 "TMUs")
6 RBEs -> 24 "ROPs"

And the card will be red...



EDIT:
7 x 80-SPU blocks = 560 x 3 Flops x .625GHz -> 1050 GFlops, 28 "ROPs"
6 x 96-SPU blocks = 576 x 3 Flops x .625GHz -> 1080 GFlops, 24 "ROPs".
6 x 128-SPU blocks = 768 x 2 Flops x .625GHz -> 960 GFlops, 24 "ROPs".

 

[nexus_alpha]

Are you talking about the legendary ATi chip, which will be revealed in approximately 6 months ?

I known where you live

 

[Wirmish]

I known where you live

I said nothing, I swear, don't kill me !

 

[Mat3]

The unused tesselation unit would be one candidate.

The tesselator unit "uses only a small amount of die", so even if they dropped it, that wouldn't give them much more to work with.

I bet they continue supporting it.

 

[Wirmish]

Who told you guys there wasn't a shader clock? 0_o Ofcourse there is, and its higher than the core clock. (link)

Perkam

Shader clock, no shader clock, shader clock, no shader clock, shader clock, no shader clock, shader clock, no shader clock, ...

I'm gonna go crazy !
Need some rest...

 

[Nuker]

Well, G80 had less than R600, but then reality set in. Same for G92 vs RV670.
Remember that theoretical teraflops numbers don't mean much unless there an actual advantage in real-world applications.

Still, let's wait and see what RV770 can do. It sure looks promising.

I think the R600 had less than G80 didn't it? 8800U is at somewhere like 580 Gflops, with 350 is the real theoretical number (due to lacking utilization of the MUL-unit).

 

[ninelven]

Well, even ignoring the SFU, 64 x 4 x 2 x .742 = 380 GFlops for the 2900XT.

 

[Nuker]

The X1900XTX has been said to be more than 500 Gflops each though...

 

[ninelven]

Well, 426.6 GFlops according to Beyond3D .

 

[Nuker]

Yeah I have heard both that and 500+, but 400 seems much more reasonable.

 

[Kaotik]

http://i114.photobucket.com/albums/n273/Wirmish/GPU-Dies.png

RV670 -> 14,36 mm x 13.37 mm = 192 mm²
RV770 -> 15.65 mm x 15.65 mm = 245 mm²
G92b ---> 16.4 mm x 16.4 mm = 268 mm²
G92 ----> 18 mm x 18 mm = 324 mm²
G200 --> 24 mm x 24 mm = 576 mm²

Hmm, wasn't the RV770 supposed to be 256mm^2

 

[Lukfi]

It's supposed to be 250 mm2 with a margin of error of 5 mm2

 

[Megadrive1988]

Slightly off-topic: I wanted to say that I think a redesigned/modified 32nm or 22nm shrink of the RV770 would make an exellent GPU for Nintendo's next console. RV770 will be concidered lowend by 2010-2011 and sub-lowend by 2012, and yet, it would provide an absolutely massive generational leap beyond Flipper & Hollywood. Now of course in actuality Nintendo wouldn't use an RV770 derivative, so what I really mean is, a GPU with RV770 level of power and features.

 

[CarstenS]

Well, even ignoring the SFU, 64 x 4 x 2 x .742 = 380 GFlops for the 2900XT.

Why would you choose to ignore the RYS_Unit?

 

[Ailuros]

The unused tesselation unit would be one candidate.

Is it really a separate unit or part of the ALUs? It's my understanding that it's more trouble to deduct those capabilities then to leave them inside after all.

As for the rest: the mistake everyone made was to immediately accept the supposed 480SPs because it made "sense" and the 800SP scenario was immediately discarded because it sounded "too much".

That whole SP marketing nonsense doesn't help that's true but let's see R6x0/RV6x0 have 4 clusters with 16 ALUs each; due to the capabilities of those ALUs the creative number of 320SPs came to life (obviously in reaction the 128SPs of the G80).

Now I calculate the theoretical floating point throughput on those as follows:

64 ALUs * 10 FLOPs = 640 FLOPs/GHz

Thus when you have 320SPs you logically have 2 FLOPs/SP.

I haven't read or heard anywhere so far that RV770 was a project that cost a ton of R&D resources, rather the opposite which makes sense considering their excellent execution for a second time in a row. In short: no ground breaking changes that consume too much time and effort.

With hypothetical 480SPs that would give 960FLOPs/GHz which means that the PRO alone would have to have something beyond 1GHz frequency or according to some funky scenarios a shader domain with as much difference. First scenario sounds unlikely (increase chip complexity and clockspeed on the same process? errr.....), the latter isn't going to come for free in terms of transistors and R&D resources.

Now if you try the speculative math with the hypothetical 800SPs it'll give you 1600FLOPs/GHz; considering the frequencies (625, 750MHz) of both boards it does sound more likely to be the correct original rumour, depsite the fact that its a nonsensical marketing number like anything else.

Something else: theoretical maximum specifications are one part of the story and efficiency or what comes out at the other end another story. There have been endless debates about the missing MUL on G8x/9x and we have seen now a revival of that saga when the first GT200 details appeared. Let's see how the theories will look like after the RV770 launch (since it'll arrive slightly later).

As for the double precision/GPGPU stuff: R6x0/R6x0 already seemed to do a lot better than their competing parts in that department. From a technical POV there's definitely some interest, but as a gamer my buying decision won't have anything to do with those capabilities.

 

[LordEC911]

Ummmm.... New RV770 slide?

 

[w0mbat]

Never ever smoke in the bed... ähm post w/o source: http://www.nordichardware.com/news,7841.html

 

[Raqia]

Well there's certainly one way of solving the AA problem... by throwing a lot more shaders at it. It would explain why driver development is taking so long too. Does that mean we stay 16 TMUs? How would they cram in so many more shaders and still increase TMU counts? What does this mean for the budget parts?