Hey Bleem - just wanted to point out that no one thinks you were talking retail price here - we're talking manufacturing costs. The expectation of 50% cost reductions is simply too great. When the Falcon story broke a couple of days ago, along with it broke the notion that Microsoft would be able to shrink the chips by 50%. BUT, that's just a hypothetical marker - to get a real-world sense of what the savings might be, you need to factor in what the actual die size is (because node shrinks don't always - in fact rarely - go to the straight halving) and what the yields are. And obviously those two chips are only a piece of the puzzle in terms of manufacturing costs; the rest of the components are affected in a cascading fashion, but it's not the same geometric halving that is even theoretically possible on the silicon, so guessing at it is much more nuanced.
EDIT: Wanted to add here a favorite slide of mine, showing what we rarely get to see - a die migration across an entire generation. Note how even within process generations, further revision refinement still gets done. And note of course how with the traditional Moore's Law node shrinks, it never goes exactly to 50%. This is for Sony and Toshiba on the CMOS process rather than MS and their work with TSMC - no fab process is identical. But it gives an idea of how varied these things can be... much moreso than simply soundbites extolling Falcon at 65nm as some cut-and-dry thing automatically halving the cost of the chips.
The EE+GS itself has of course been further refined since that slide was released.