Xbox One (Durango) Technical hardware investigation
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It's 102 GB/s bidirectional bus, not separate 51 GB/s up and down buses.
You miss-read it.The ESRAM bus is 102.4 GB/s. the table showing 51.2 GB/s read and write is if you are moving data from ESRAM to ESRAM, and is there to compare the transfer speeds around different pools. ESRAM to DRAM is 68.2 GB/s, meaning 68.2 GB/s read from the ESRAM. If you were doing pure read from ESRAM, it's 102.4 GB/s, and the same for pure writes, so the bus is, as specified in the tech docs, 102.4 GB/s in BW, accounted for by 800 MHz * 128 bytes per clock.
There is no simultaneous read/write listed anywhere in the tech docs. The bus isn't bidirectional* and technically cannot exceed its 102.4 GB/s total BW. This rumour flies in the face of the computer architecture, and cannot be explained simply.
* I think I'm misusing that term. A bidirectional bus works both ways, so shares its total BW between reads and writes. The word I mean is to describe reading and writing simultaneously, which I can't think of the name of in computer architecture terms!
Duplex, like in telecom. The terms would basically work: simplex, half duplex, duplex. A bus as we know it would be bidirectional simplex.
Danke Sir
Yeah, you're right, but those terms don't ring a bell regards system buses. I wonder if all computing buses are simplex, hence no-one's bothered to worry about terminology?
They are saying that its full duplex in certain cases with an 88% increase due to efficiency which brings it down from 204.8 gb/s to 192.512 gb/s. 102.4*1.88= 192.512.
I've gotten some PMs here and at Neogaf talking about a modest upclock for the xbox one. The 4 messages I received from 4 different accounts ( could be the same person but some of them are accounts from years ago) all state 75mhz for the gpu at this stage and it may go up slightly more.
I don't know how accurate this is. But perhaps this is where the increase in bandwidth is really coming from and MS simply wont ever announce clock speeds for the chip ?
I don't know how accurate this is. But perhaps this is where the increase in bandwidth is really coming from and MS simply wont ever announce clock speeds for the chip ?
itsmydamnation
Veteran
people are making stuff up here so to speak. the very vast majority of "telecom" technologies have dedicated pins/frequencies for there tasks. The only exception i'm aware of is 1000BASE-T where traffic is sent an received on all pins and algorithum is then used to remove the noise from the collision that just occurred. This can be done because the NIC is aware of what it just sent so simplistically its C=A+B. That said its also only running at 100mhz.
arijoytunir
Regular
is it 875mhz ? also does'nt upclocking a cpu or gpu shorten its lifespan ?
yea that's what they said to me. And no it shouldn't shorten anything. Will a radeon 7970 die faster than a 7950 ? Same chip just different speeds.
you should say who, or at least pm me the names :0 i can probably have a decent idea just from who it is if it would have any validity whatsoever.
i'd be wary though. i've heard nothing of that. the clock seem terribly stubborn at 800/1.6, through it all, there they've remained (afaiwk)
they might even be trying to bait you into posting it on gaf and getting banned. that's what they did to reiko...actually i'd say that's the most likely case.
that upclock isn't enough for the bw increase, if it was tied to clock. it's be ~10% increase, or ~110 gb/s.
arijoytunir
Regular
i think the 800mhz and 1.6ghz is the sweetspot for power consumption .
that is why they must be sticking to it .
Can one of the more technically minded members explain what is proposed in the linked page
http://memoir-systems.com/index.php/technology
Thanks in advance.
http://memoir-systems.com/index.php/technology
Thanks in advance.
I don't buy that. The bus width would have to double and it would increase the complexity of the logic.
I'd think so. In telecom a simplex connection is normally unidirectional, as far as I know. Just thought the terminology could help in this discussion, because busses are read/write bidirectional but can't do both at the same time. Duplex, simplex is a good way to differentiate.
I just meant to borrow the terminology, not imply there is any kind of technology borrowed from telecom transceivers.
Yep. I think I'm confusing things. AFAIK buses are limited to one bit of info in one direction per clocks. Dealing with two signals on one wire in opposite directions at the same time can't be easy, especially at electronics frequencies and component sizes.
Yeah, but 'duplex' isn't really viable. No bus sends and receives data simultaneous in electronics, so the idea that the GPU<>ESRAM BUS can do this is extraordinarily unrealistic AFAIK.
The only obvious way to get more info across the same bus at the same clock speed is to do something funky with the clocks and manage to squeeze an extra 'cycle' in there (or rather, on the down cycle send info one way, and on the up signal send data the other way). That's not something you'd just come across by chance though! If it's even possible.
QualityAssurance
Newcomer
So the BW increase is a result of adding read/write speeds to ESRAM? I didn't know bi-directional busses were a real thing.
And by bi-directional, I mean the ability to read/write at the same time.
And by bi-directional, I mean the ability to read/write at the same time.
No, this is getting very muddled!
The BW between XB1's GPU logic and ESRAM is 128 bytes wide at 800 MHz. It can send 128 bytes per clock in either direction. The peak BW is 102.4 GB/s, which you could spend all on reading from the ESRAM, or all 102.4 GB/s writing to the ESRAM, or split between reading and writing. If reading and writing to the ESRAM with a workload, logically the split is 51.2 GB/s.
XB1's bus cannot send and receive data simultaneous in the same clock (as far as we know).
The BW between XB1's GPU logic and ESRAM is 128 bytes wide at 800 MHz. It can send 128 bytes per clock in either direction. The peak BW is 102.4 GB/s, which you could spend all on reading from the ESRAM, or all 102.4 GB/s writing to the ESRAM, or split between reading and writing. If reading and writing to the ESRAM with a workload, logically the split is 51.2 GB/s.
XB1's bus cannot send and receive data simultaneous in the same clock (as far as we know).
Betanumerical
Veteran
I was thinking that maybe the extra bandwidth confusion comes from the compression/new stuff that GCN does that means even with 102.4GB/s of bandwidth you get '133GB/s' of equiv uncompressed bandwidth based off stuff like MSAA compression and what not.
This is a complete shot in the dark though.
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