One More Time From The Top
I do not know if AMD is using "true" SRAM or if they are using 1T SRAM which is really eDRAM. There are many types of DRAM that has additional support circuitry so that it "looks" much like SRAM.
I doubt anyone posting here knows. But 1T-SRAM that has been publicly announced for the likely processes/fabs sounds like a good bet. In other words eDRAM in truth.
It has been covered in other posts, but:
Embedding memory on the ASIC or processor allows for much wider buses and higher operation speeds, and due to much higher density of DRAM in comparison to SRAM, larger amounts of memory can be installed on smaller chips if eDRAM is used instead of eSRAM. eDRAM requires additional fab process steps compared with embedded SRAM, which raises cost, but the 3X area savings of eDRAM memory offsets the process cost when a significant amount of memory is used in the design.
eDRAM memories, like all DRAM memories, require periodic refreshing of the memory cells, which adds complexity. However if the memory refresh controller is embedded along with the eDRAM memory, the remainder of the ASIC can treat the memory like a simple SRAM type such as in 1T-SRAM.
eDRAM is used in IBM's POWER7 processor[1] and in many game consoles and other devices, including Sony's PlayStation 2, Sony's PlayStation Portable, Nintendo's GameCube, Nintendo's Wii, Nintendo's Wii U, Apple Inc.'s iPhone,
Microsoft's Zune HD, and Microsoft's Xbox 360.
1T-SRAM is a pseudo-static random-access memory (PSRAM) technology introduced by MoSys, Inc., which offers a high-density alternative to traditional static random access memory (SRAM) in embedded memory applications. Mosys uses a single-transistor storage cell (bit cell) like dynamic random access memory (DRAM), but surrounds the bit cell with control circuitry that makes the memory functionally equivalent to SRAM (the controller hides all DRAM-specific operations such as precharging and refresh). 1T-SRAM (and PSRAM in general) has a standard single-cycle SRAM interface and appears to the surrounding logic just as an SRAM would.
Due to its one-transistor bit cell, 1T-SRAM is smaller than conventional (six-transistor, or “6T”) SRAM, and closer in size and density to embedded DRAM (eDRAM). At the same time, 1T-SRAM has performance comparable to SRAM at multi-megabit densities, uses less power than eDRAM and is manufactured in a standard CMOS logic process like conventional SRAM.
MoSyS markets 1T-SRAM as physical IP for embedded (on-die) use in System-on-a-chip (SOC) applications. It is available on a variety of foundry processes, including Chartered, SMIC, TSMC, and UMC. Some engineers use the terms 1T-SRAM and "embedded DRAM" interchangeably, as some foundries provide Mosys's 1T-SRAM as “eDRAM”. However, other foundries provide 1T-SRAM as a distinct offering.
1T SRAM is built as an array of small banks (typically 128 rows × 256 bits/row, 32 kilobits in total) coupled to a bank-sized SRAM cache and an intelligent controller. Although space-inefficient compared to regular DRAM, the short word lines allow much higher speeds, so the array can do a full sense and precharge (RAS cycle) per access, providing high-speed random access. Each access is to one bank, allowing unused banks to be refreshed at the same time. Additionally, each row read out of the active bank is copied to the bank-sized SRAM cache. In the event of repeated accesses to one bank, which would not allow time for refresh cycles, there are two options: either the accesses are all to different rows, in which case all rows will be refreshed automatically, or some rows are accessed repeatedly. In the latter case, the cache provides the data and allows time for an unused row of the active bank to be refreshed.
There have been four generations of 1T-SRAM:
Original 1T-SRAM
About half the size of 6T-SRAM, less than half the power.
1T-SRAM-M
Variant with lower standby power consumption, for applications such as cell phones.
1T-SRAM-R
Incorporates ECC for lower soft error rates. To avoid an area penalty, it uses smaller bit cells, which have an inherently higher error rate, but the ECC more than makes up for that.
1T-SRAM-Q
This "quad-density" version uses a slightly non-standard fabrication process to produce a smaller folded capacitor, allowing the memory size to be halved again over 1T-SRAM-R. This does add slightly to wafer production costs, but does not interfere with logic transistor fabrication the way conventional DRAM capacitor construction does.
I think the truth is that the eSRAM people are taking about is the exact same 1T-SRAM (eDRAM) that IBM is taking about. I expect it is the same cells in the same foundries in the same process. I might be wrong but I don't think so.
I do not know if AMD is using "true" SRAM or if they are using 1T SRAM which is really eDRAM. There are many types of DRAM that has additional support circuitry so that it "looks" much like SRAM.
I doubt anyone posting here knows. But 1T-SRAM that has been publicly announced for the likely processes/fabs sounds like a good bet. In other words eDRAM in truth.
It has been covered in other posts, but:
Embedding memory on the ASIC or processor allows for much wider buses and higher operation speeds, and due to much higher density of DRAM in comparison to SRAM, larger amounts of memory can be installed on smaller chips if eDRAM is used instead of eSRAM. eDRAM requires additional fab process steps compared with embedded SRAM, which raises cost, but the 3X area savings of eDRAM memory offsets the process cost when a significant amount of memory is used in the design.
eDRAM memories, like all DRAM memories, require periodic refreshing of the memory cells, which adds complexity. However if the memory refresh controller is embedded along with the eDRAM memory, the remainder of the ASIC can treat the memory like a simple SRAM type such as in 1T-SRAM.
eDRAM is used in IBM's POWER7 processor[1] and in many game consoles and other devices, including Sony's PlayStation 2, Sony's PlayStation Portable, Nintendo's GameCube, Nintendo's Wii, Nintendo's Wii U, Apple Inc.'s iPhone,
Microsoft's Zune HD, and Microsoft's Xbox 360.1T-SRAM is a pseudo-static random-access memory (PSRAM) technology introduced by MoSys, Inc., which offers a high-density alternative to traditional static random access memory (SRAM) in embedded memory applications. Mosys uses a single-transistor storage cell (bit cell) like dynamic random access memory (DRAM), but surrounds the bit cell with control circuitry that makes the memory functionally equivalent to SRAM (the controller hides all DRAM-specific operations such as precharging and refresh). 1T-SRAM (and PSRAM in general) has a standard single-cycle SRAM interface and appears to the surrounding logic just as an SRAM would.
Due to its one-transistor bit cell, 1T-SRAM is smaller than conventional (six-transistor, or “6T”) SRAM, and closer in size and density to embedded DRAM (eDRAM). At the same time, 1T-SRAM has performance comparable to SRAM at multi-megabit densities, uses less power than eDRAM and is manufactured in a standard CMOS logic process like conventional SRAM.
MoSyS markets 1T-SRAM as physical IP for embedded (on-die) use in System-on-a-chip (SOC) applications. It is available on a variety of foundry processes, including Chartered, SMIC, TSMC, and UMC.
Some engineers use the terms 1T-SRAM and "embedded DRAM" interchangeably, as some foundries provide Mosys's 1T-SRAM as “eDRAM”. However, other foundries provide 1T-SRAM as a distinct offering.1T SRAM is built as an array of small banks (typically 128 rows × 256 bits/row, 32 kilobits in total) coupled to a bank-sized SRAM cache and an intelligent controller. Although space-inefficient compared to regular DRAM, the short word lines allow much higher speeds
, so the array can do a full sense and precharge (RAS cycle) per access, providing high-speed random access. Each access is to one bank, allowing unused banks to be refreshed at the same time. Additionally, each row read out of the active bank is copied to the bank-sized SRAM cache. In the event of repeated accesses to one bank, which would not allow time for refresh cycles, there are two options: either the accesses are all to different rows, in which case all rows will be refreshed automatically, or some rows are accessed repeatedly. In the latter case, the cache provides the data and allows time for an unused row of the active bank to be refreshed.There have been four generations of 1T-SRAM:
Original 1T-SRAM
About half the size of 6T-SRAM, less than half the power.
1T-SRAM-M
Variant with lower standby power consumption, for applications such as cell phones.
1T-SRAM-R
Incorporates ECC for lower soft error rates.
To avoid an area penalty, it uses smaller bit cells, which have an inherently higher error rate, but the ECC more than makes up for that.1T-SRAM-Q
This "quad-density" version uses a slightly non-standard fabrication process to produce a smaller folded capacitor, allowing the memory size to be halved again over 1T-SRAM-R. This does add slightly to wafer production costs, but does not interfere with logic transistor fabrication the way conventional DRAM capacitor construction does.
I think the truth is that the eSRAM people are taking about is the exact same 1T-SRAM (eDRAM) that IBM is taking about. I expect it is the same cells in the same foundries in the same process. I might be wrong but I don't think so.
