The G92 Architecture Rumours & Speculation Thread

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But GF7800 was high-end part. NV42 and G92 (according to many sources) are midrange products.

Not to mention the fact that the 6800GS (PCI-e version) was actually on par or faster than the 6800GT. The former had 12 pipelines, while the latter had 16.

256bit bus, 512mb (8 memory chip configuration then?)

GDDR4 could also lower power consumptions, and with a memory clock of 2GHz, it would have the exact same bandwidth of a GTS. (Agreeing AnarchX's predictions on the core clock and memory speeds).

Dual precision? Dual MADD? or ALU side of things remain the same?
 
But GF7800 was high-end part. NV42 and G92 (according to many sources) are midrange products.

Yeah, my point was that the high-end refresh came before the mid-range refresh last time. There has been no high-end refresh this time.
 
Well, if VR-Zone's numbers for the texture fillrate are correct, then I'm not sure G92 is really a NV42 equivalent. If they use GDDR4 on that supposed 256-bit bus and have higher ALU performance than G80, then I'm sure they could match at least a 8800 GTX or do even better than that. Especially so since the clock rate seems to be 750MHz+, which means 30%+ higher than the 8800 GTX.
 
That's a SKU though, not a new chip... I don't think it really counts for what we are thinking of here - although it'd be interesting to know if it was originally supposed to be based on the G81 or something along these lines.
 
My guess is that diagram is just wrong, because neither 1000M nor 500M would really make much sense. But I could be mistaken...
 
My guess is that diagram is just wrong, because neither 1000M nor 500M would really make much sense. But I could be mistaken...

Why would make 500M no sense for G92?

Transistor-difference(one cluster) between G84 und G86 is 79M and G92 is said to be a cheaper 8800GTS-replacement and there are rumours about 800MHz in the net.

So I would guess that G92 has 4 clusters@800MHz(2GHz+ SD), which result in ~88GTS-performance.

289M + 2*79M = 447M + 2 rop-clusters + DP + VP3 (+ D3D10.1 (rumored to be compliant by all G8x or not supported by first G9x GPUs) - some transistor-improvements (like G70 to G71) = ~500M ;)

And to associate it with the ~1 TFLOPs-thing: 2x G92 with ~2.4GHz SD (mentioned earlier in the Beyond G80 thread and by a reliable source in recent past).
 
It looks like someone just extended the line from G70 to G80 out to G92.

I doubt one of Nvidia's design constraints was that the transistor count graph maintain an equal slope.
 
And to associate it with the ~1 TFLOPs-thing: 2x G92 with ~2.4GHz SD (mentioned earlier in the Beyond G80 thread and by a reliable source in recent past).
Or just 8 clusters instead of 4, which would collide with the VR-Zone "50 GT/s" number perfectly... But maybe I'm reading too much into that number of course! :)
 
My guess is that diagram is just wrong, because neither 1000M nor 500M would really make much sense. But I could be mistaken...

Why not ~1000M? With the shrink from 90nm to 65 you could put 1000M and still have a die size of ~350mm no?
 
Why not ~1000M? With the shrink from 90nm to 65 you could put 1000M and still have a die size of ~350mm no?
Yes, but the data point I'm considering here is 256-bit... Does it really make sense to have a ~350mm2 chip with a 256-bit bus when they could have a 320-bit one with that, or even more? Presumably the die size has to be between 200 and 300mm2 for it to make sense IMO...
 
Wrong, I bet 100% that G92 will be a cut-down version of G80 with slightly improvement. And it could be faster than 8800GTS.


G92, in terms of the package, will be similar to Q6600, However, the another problem shall be solved before the launch of the G92. such as limitation of the TMU.


ATI must be cautious that Nvidia will no longer playthe role for the Super-High End, as to the refreshing product shortly after the G80.
 
Yes, but the data point I'm considering here is 256-bit... Does it really make sense to have a ~350mm2 chip with a 256-bit bus when they could have a 320-bit one with that, or even more? Presumably the die size has to be between 200 and 300mm2 for it to make sense IMO...

It could be two dies in one package board.
 
Two-die-packages does not make much sense for graphics-cards, because here you could make solutions with two simple PCBs and so better spreaded heat sources.

And from two seperated dies with only one MC we are far away.

Or just 8 clusters instead of 4, which would collide with the VR-Zone "50 GT/s" number perfectly... But maybe I'm reading too much into that number of course! :)
I heard, that these ~50GT/s are maybe serious. ;)
But the question is, by what they are reached? Sure there could be a 8 cluster GPU with 0.8/2.4GHz clocks, but I doubt it would be called G92 and has only a 256Bit MC (an appropriate bandwidth to this 50GT/s would need 2GHz memory).
 
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Two-die-packages does not make much sense for graphics-cards, because here you could make solutions with two simple PCBs and so better spreaded heat sources.

And from two seperated dies with only one MC we are far away.



Well, let the time tell.
 
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