The AMD Execution Thread [2018]

Doesn't rule out making a lot of Vega without the memory being available. If it were Vega, a simple rebate or promotional offer would fix the issue. Perhaps even push them into the server market.

Low or mid tier Polaris may make sense as they were the ideal mining platform for some time. Ample supply for gamers on a budget if miners are dumping there. Second hand Vegas likely eating into the new Polaris market.

 

Interestingly, here in germany, even with an apparent surplus of GPUs (may they be Vega or not), Vega prices did not drop below the intial rebated 399 EUR for the V56. V64 otoh, moved down from their advertised launch price about 30 EUR to 469. When I see the recently really great deals on nearly everything that is Polaris (an 8 GB 570 for 170 EUR for example), I cannot help but think that the combination of Interposer, HBM2, PCB and necessary components (so BOM basically) do not allow for prices below that range without (major?) loss.

 

I think Lisa indicated they will let it work through the system. Makes sense since there will be no *new* products introduced for a bit and these are expected to be their primary GPU products for the next couple quarters.

 

That or there is no reason to lower price at this point in time. Major loss is a product that can't be sold. Only an issue if they produced enough already to carry them through Navi or a 7/12nm Vega refresh we haven't seen mentioned yet. Ignoring Vega20 as it's not a gaming part.

That doesn't really constitute an inventory problem if they plan on selling everything normally without putting off another product launch. That being the case, this may just be a story that got out of hand.

 

Those who buy stocks on hope and emotion are not investors but speculators.

 

[edited]

 

AMD's "Next Horizon" event next week:

https://www.anandtech.com/show/13538/amd-investor-relations-next-horizon-november-6th

Stuff that might get mentioned:

- Polaris 30 RX590
- Zen 2 details
- Vega 20
- Navi ?
- ?

 

As tehy mentioned a datacenter focus, Polaris and navi won't be big topics there. Vega20 release and Zen2 details is my best guess. Navi details will probably be presented at the CES keynote.

 

May be due for an updated roadmap. So Navi and possibly beyond in addition to Zen. Probably some mention of the mobile Vegas that recently showed up along with some APUs. Still haven't seen a KabyG style product from AMD. Even if it's designed around GDDR or a more affordable memory for notebooks or consoles.

 

You mean those for the roadmap?
I doubt AMD has even planned any "KabyG-style product" - they can do bigger APUs if they so choose so there would be little incentive to do MCM (I'm sure Intel would have loved to have KabyG in a single chip (+separate HBM stack of course) but that wasn't an option for them). AMD also mentioned several times over that Kaby isn't stepping on toes of any of their (planned) products. Also, doing MCM but using GDDR instead of HBM wouldn't really save that much space from the motherboard.

 

Being investor oriented, updating on any planned products would be rather basic. Mostly stuff we already know, but maybe a generation further. Stuff beyond 2020 etc, even if in codename only.

I agree on the bigger APU, but it could work as MCM as well. What I was getting at is they need to address the APU bandwidth issue for higher performing parts. Realising a mass market "console" might be practical. HBM is another possibility. KabyG, with shared memory, should be possible and not necessarily step on toes for AMD. GDDR would be a bandwidth play, not space.

I still like the KabyG idea with two GPUs for the purpose of sandboxing and security. Google has been doing a lot of work on ChromeOS for GPU pass through. There are codenames for AMD based Chrome products, just nothing on the market. That could be a roadmap item or product with financial consequences. Assuming it's not a semi-custom product for Google.

 

Amd is gaining traction in supercomputing for their cpu's.

https://www.tomshardware.com/news/amd-epyc-milan-shasta-exascale,38067.html

 

I did not see that one coming. I'm not sure there's all that much money in this deal, but it sure is great PR, and a good sign about Milan.

 

German HLRS is also using AMD CPUs for their new flagship supercomputer "Hawk". It'll be built using 10 000 Epyc Rome CPUs

https://www.anandtech.com/show/13598/amd-64-core-rome-deployment-hlrs-hawk-at-235-ghz

 

Money or profit is difficult to quantify because of the research grants involved. Still, that's an impressive machine that isn't all that surprising considering AMDs IO and memory advantage with Epyc.

 

Well, yeah, but the flip-side is that they've been a bit behind in FP workloads due to low AVX throughput, at least with Naples. Romes doubles that, but it's still limited to AVX-2. On the other hand, it has a lot of cores and it may be able to sustain decent clocks with AVX-2, thanks to its 7nm process.

I'd be curious to know what decided this contract: the factors mentioned above, or added support for AVX-512 in Milan, or expected gains from 7nm+ (EUV)…? I guess it will be another year or so before AMD starts revealing anything of substance about Milan, however.

 

May depend on the workloads. AVX may not be as important with all the GPU flops. Leaving the PCIe4 bandwidth, extra system memory, and likely affordability/density compared to Intel's solution. Even CPU power would be a small portion of total system power with all those GPUs. So 7nm EUV helps, but is of limited usefulness.

With the IO die it's also possible there are solutions with far more IO available. Having 16 memory channels and/or NVDIMMs should be doable. Along with OpenCAPI support, which seems likely. There could be more integration with other accelerators than is apparent.

 

Sure, but I think there's still a significant chunk of HPC workloads that are purely CPU, although I could be wrong about that.

Are you referring to the possibility of an upgraded IO die in Milan, or to undisclosed IO in the current one? In the former case, that's a possibility, but it would require some (difficult) shrinkage, as the current IO die is already huge, and there's not much more space available on the package. In the latter case, I don't think AMD would leave anything hidden/disabled in Rome. So barring anything really exotic about the process used for the IO die, I don't really see any way to scale things up on the IO front. Besides, AMD might want more cores for Milan, which would mean bigger chiplets, hence even less space available for the IO die.

 

its an interesting concept a HPC I/O die.

Given that it would largely just be more of the same and generally on an older process, the cost to do so would be on the low end. I could totally see something like that for milian.

The other interesting bit is being able to decouple I/O die refresh with chiplet refresh.

 

I'm fairly sure that system has CPU-only cabinets so CPU power is still important.

Or semi-custom I/O die for our favourite hyperscale friends.