Obviously interconnects have to be there no matter if it's "empty silicon" or not to get data from A to B through it, what I meant is that there's no logic and if the PHYs didn't already dictate the die size to be what it is, those spaces could have probably been trimmed off the chip making it cheaper (so no, I don't think the space there is necessary for the routing, but it's there only because the PHYs are making the chip so big).
The new standards will need new logic for sure, but how much? Getting new stuff might mean more and/or bigger PHYs to fit in too. Moving to smaller process, while it would save power, might make them too expensive too, if it requires "wasted silicon" to fill the void. And then, in context on desktop and servers, do we even need the power savings? I mean, that IO die is 20 watts - how much scraping, say, 10 watts from it to be used by cores instead would help? In mobile where power savings matter more they're continuing to use monolithic designs for now anyway.