You and Capeta are viewing things in way too PC-centric a manner, as if the rest of the world of semiconductors is 'meh' because we don't read about it on tech sites every day. You haven't answered my question yet Deusp as to why companies like AMD and IBM need advanced fabs, so I'm still waiting on that - personally I don't think there's any logic that can be applied there that will be exclusive to those companies. Why shouldn't AMD just outsource everything to Chartered and stop making their own fabs? Indeed, it will be interesting to see what node the chips inside the iPhone do indeed use - Capeta guesses 90nm... perhaps. But it's a lot more likely to be 65nm than 130nm for instance, agreed?
I can't speak to the entire range of reasons why a company would decide one way or the other, but IBM and AMD do have a more pressing demand for a very specific subset of high-performance processes.
I've seen discussions and articles indicating that high-end MPU processes are very targeted, which makes them less suitable for analog and specialized products.
Analog doesn't really scale anyway, but it's a given that any non-MPU product on a high-end process like AMD's would be leakier, hotter, and less reliable (assuming it can work as designed). Analog and mixed signal hardware is casually brushed aside on such processes.
IBM and AMD are also subject to a constraint that circuit performance at the next process node improve over the last. TI's dropping out of the scaling race in processes like those used by Sun's processors is a symptom of the end of this trend.
One need only look at Intel's 45nm process to see that heroic efforts are needed to maintain a performance improvement.
For a current example, look at the currently nonexisted clock speed gains AMD got from shifting to 65nm production. The highest clocking chips are 90nm.
In other designs, the already subnominal density scaling high-speed logic gets from process transitions is getting worse, because the densest circuits do not perform as well.
65nm may be what will be known in the future as the end of guaranteed performance scaling by process transition.
CCDs don't need to worry about maintaining gigahertz clock speeds.
Non MPUs can benefit from less performant processes, because they need only care about density or power consumption.
(edit to word this better: their power and density constraints restrict their need for circuit performance to well within the range offered by a less performance-driven process)
While future nodes will be expensive, future high-performance nodes are even more so.
Worse, high-performance nodes cater to a very limited market compared to the rest of the IC world.
This is also a reason why IBM's cooperative strategy may not win against Intel in the MPU space. Every partner has a certain ideal process, which leads to a more general and less optimized solution.
It's one of the reasons why foundry chips clock so far below in-house fabs. The more general needs of a TSMC foundry's client range means a number of circuit types and safety margins that can be removed or smoothed over with an Intel process must be present, even if at the cost of longer timings.
Realworldtech had an article that put timings for a foundry at 2-3x those of an Intel one.
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