IBM, Sony and Toshiba extends the chip alliance toward 32nm

[one]

PS4 to arrive in 2011?

http://www.sony.net/SonyInfo/News/Press/200601/06-0112E/index.html

IBM, Sony, Toshiba Broaden and Extend Successful Semiconductor Technology Alliance
Agreement Now Includes Early-Stage Research on Critical Emerging Technologies Targeted at 32 Nanometer (nm) Generation and Beyond

TOKYO, JAPAN and ARMONK, NY - January 12, 2006 - IBM, Sony Corporation and Toshiba today announced they have begun a new, five year phase of their joint technology development alliance.

As part of this broad semiconductor research and development alliance, the three companies will work together on fundamental research related to advanced process technologies at 32 nanometers and beyond. The agreement will help enable the three companies to more rapidly investigate, identify and commercialize new technologies for consumer and other applications.

 

[Shifty Geezer]

They have to, to counteract SEGA Sammy's re-emergency with their uber console...

Or more honestly, no. Sony want 6/7 year cycles. They and Nintendo felt this gen is being rushed out the door.

Though in theory yes, because with the groundwork for Cell covered already, a next-gen console could just be PS3 type innards on smaller processes to fit more in.

So in summary - who knows?

 

[Titanio]

Good news. Highly obvious, but good that it's confirmed.

I'd say PS4 won't "simply" be more current Cells. Maybe "son of Cell"

Also:

Research and development will take place at IBM's Thomas J. Watson Research Center in Yorktown Heights, N.Y., the Center for Semiconductor Research at Albany NanoTech, and at IBM's 300 millimeter manufacturing facility in East Fishkill.

No mention of Austin?

The release seems to suggest a broadening and deepening of the relationship, but it's a little low on specifics..

 

[Titanio]

There are a few articles out there with commentary, and further comments from IBM and Sony:

http://www.thestreet.com/_googlen/tech/semis/10261454.html?cm_ven=GOOGLEN&cm_cat=FREE&cm_ite=NA

Under the agreement, the three companies will collaborate on future versions of the Cell microprocessor to be based on 32-nanometer processing technology. The current Cell relies on 90-nanometer technology and the existing road map for the processor goes only as far as 65 nanometers.

The collaboration also will explore the use of new types of semiconductor materials and other underlying technologies, which could lead to new chips and products beyond the Cell.

"We're looking for the next big processor breakthrough," said Lisa Su, vice president of IBM's Semiconductor Research and Development Center. The latest phase of the alliance will put a great deal of emphasis on early-stage research, whereas the previous effort focused more on development, said Su.

http://www.businessweek.com/technology/content/jan2006/tc20060112_858674.htm

Now the partners jointly plan to develop breakthrough semiconductor designs and materials that will enable the next generation of Cell processors -- plus other chips -- to fit on ever-smaller pieces of silicon. The work will happen at IBM's Yorktown Heights Research Center and at its advanced chip-fabrication plant and the government-backed Albany Nanotech Center both in New York. "We're doing fundamental research," says Lisa Su, vice-president for semiconductor R&D at IBM. "People don't know how to do this yet."

Analysts hailed the announcement as an important event in the annals of the tech industry. They expect the partners to spend several hundred million dollars, at least, over the next five years.

"This is the first public commitment by anybody in the world to 32-nanometer technology," says Richard Doherty, director of the market research firm Envisioneering Group.

http://www.forbes.com/markets/feeds/afx/2006/01/12/afx2444657.html

Yoshikazu Ochiai, a Sony spokesman, said the new alliance is meant to replace the previous collaborative arrangement.

 

[Entropy]

Good news. Highly obvious, but good that it's confirmed.

I'd say PS4 won't "simply" be more current Cells. Maybe "son of Cell"

Out of personal interest - where would you like to see the current design go, assuming some 5 times greater transistor budget?
As it stands, the design seems quite scaleable, so it could "simply" be multiplied by four, with beefed up data paths to allow for the corresponding increase in processing power and data flow, and added nips and tucks where real life usage patterns showed bottlenecks to occur.

The reason I ask is that this processor looks pretty well tuned to its primary application space, and the basic ethos of cell processing is that you should spend your transistors strenghtening parallell processing capabilities rather than going too far into the land of diminishing returns beefing up single thread performance.

But opinions differ and the real world doesn't always play nice with design principles, however reasonable.

So should a "son of Cell" instead spend more of its transistor budget to for instance:
- support fp64 fully (arithmetic units and data paths)?
- add extensive OOO capabilities to help with badly scheduled code?
- integrate specific coprocessor capabilities? (which?)
- ??

Or should it instead focus on the parallell side of life and:
- add architectural enhancements to its parallell processing capabilities?
- change vector pipe length?
- shift the PPE/SPE balance around? Fewer/More SPEs per PPE?
- ??

This chip is the first of its kind, so it would be strange if they left the architecture untouched for a new generation, but the codes I know well isn't really the primary target of the architecture, so I'm at a loss to predict what direction they would take it if they made a major overhaul. Since substantial usage data haven't had time to accumulate yet, it seems free-for-all speculation is the order of the day. Have at it.

(It may of course also be that they would primarily use the increased density to drastically reduce die sizes, costs and presumably power draw, and ensuring that all tools fit perfectly. That would make some sense too of course, but doesn't make for interesting speculation.)

 

[pc999]

Thanks for the info.

 

[London Geezer]

What are the manufacturers going to do when they reach silicon's smallest possible process (can't remember what size it actually is)?

Still haven't heard of any commercially viable alternatives, but they must be preparing themselves for the jump cause it's not TOO far away... Unless i got my maths completely wrong, which is highly possible.

 

[Shifty Geezer]

Good news. Highly obvious, but good that it's confirmed.

I'd say PS4 won't "simply" be more current Cells. Maybe "son of Cell"

That to me doesn't make as much sense. Having developed a supposedly wonderfully scaling architecture, and with devs having had 5+ years work on writing for Cell to understand, I wouldn't want to change the way it works or runs. I guess upping the LS to 512 Kb or something similar without impacting the way Cell works fundamentally would still allow BC and legacy support while allowing greater flexibility for Cell2 specific code. But moving away from something like 1 or more PPEs+lots of SPE's is going to ask of your devs to relearn yet more architecture. I don't think the hardware benefits of not going with a straight multi-Cell approach would be worth the probable software losses.

 

[Nite_Hawk]

Out of personal interest - where would you like to see the current design go, assuming some 5 times greater transistor budget?
As it stands, the design seems quite scaleable, so it could "simply" be multiplied by four, with beefed up data paths to allow for the corresponding increase in processing power and data flow, and added nips and tucks where real life usage patterns showed bottlenecks to occur.

The reason I ask is that this processor looks pretty well tuned to its primary application space, and the basic ethos of cell processing is that you should spend your transistors strenghtening parallell processing capabilities rather than going too far into the land of diminishing returns beefing up single thread performance.

But opinions differ and the real world doesn't always play nice with design principles, however reasonable.

So should a "son of Cell" instead spend more of its transistor budget to for instance:
- support fp64 fully (arithmetic units and data paths)?
- add extensive OOO capabilities to help with badly scheduled code?
- integrate specific coprocessor capabilities? (which?)
- ??

Or should it instead focus on the parallell side of life and:
- add architectural enhancements to its parallell processing capabilities?
- change vector pipe length?
- shift the PPE/SPE balance around? Fewer/More SPEs per PPE?
- ??

This chip is the first of its kind, so it would be strange if they left the architecture untouched for a new generation, but the codes I know well isn't really the primary target of the architecture, so I'm at a loss to predict what direction they would take it if they made a major overhaul. Since substantial usage data haven't had time to accumulate yet, it seems free-for-all speculation is the order of the day. Have at it.

(It may of course also be that they would primarily use the increased density to drastically reduce die sizes, costs and presumably power draw, and ensuring that all tools fit perfectly. That would make some sense too of course, but doesn't make for interesting speculation.)

Well, we already know that they are planning on speeding up the double precision floating point performance for scientific applications. I'm not sure how much of a concern that will be for the next-next generation of cell. It probably depends on how well it does in the high performance computing sector.

I imagine they probably don't know totally themselves at this point. I'm sure they are watching pretty closely what kinds of problems devs are having with it and what kinds of improvements would be best to make. I'd think we'd probably see a combination of greater numbers of SPEs, higher IO, and tweaks here and there to improve individual SPE and PPE performance. Actually, I think it will probably look somewhat similar to the kinds of advancements we see with current GPU development.

Nite_Hawk

 

[Powderkeg]

What are the manufacturers going to do when they reach silicon's smallest possible process (can't remember what size it actually is)?

Still haven't heard of any commercially viable alternatives, but they must be preparing themselves for the jump cause it's not TOO far away... Unless i got my maths completely wrong, which is highly possible.

Multiple cores. The whole reason multiple core processors are becoming so popular is the overall performance gain is greater than can be achieved by simply increasing the speed. Eventually we'll be seeing processors with hundreds, or even thousands of cores, but that will be many decades in the future and tech and programming won't be anything like it is now.

 

[Titanio]

Multiple cores

Without improved process, though, multiple cores just means greater die space, more cost, more heat etc. etc.

On that point, though, I read in one of those articles about work being done with molecular computing, working at 1 and 2nm.

Lots of good questions in this thread. It's hard to know what exactly a "next gen" Cell would look like. I'm not suggesting something totally new. I wonder if their investments going forward will be simply looking at ways to take a chip like Cell and simply cram more of them into the same space..though maybe it will be.

Shame we don't have any real idea of what Sony is targetting for their next games CPU though. I'm sure some bold proclamations will be forthcoming in due course, which might give us a better idea of what the extent of their ambition is, and what that'd require.

 

[London Geezer]

Multiple cores. The whole reason multiple core processors are becoming so popular is the overall performance gain is greater than can be achieved by simply increasing the speed. Eventually we'll be seeing processors with hundreds, or even thousands of cores, but that will be many decades in the future and tech and programming won't be anything like it is now.

I know that!
I meant, will they try to produce chips at a smaller process, using something other than silicon? Eventually they'll have to, there's only so many cores you can fit in one chip, and one day they won't be able to shrink transistors any smaller.

 

[Shifty Geezer]

Multiple cores. The whole reason multiple core processors are becoming so popular is the overall performance gain is greater than can be achieved by simply increasing the speed.

Not true. As has been said by MS, they'd have chosen a 10 GHz single core over XeCPU any day. The reason for going multicore is clockspeeds have hit a limit on current complexity, so the only way to get more power is to add more cores (assuming you're already efficient with your single-core architecture). To get more power out of a given die space and enable higher clock speeds, you can use simpler cores without any of the developer-friendly-niceties, but that's not a requirement of going multicore. If AMD could produce and run a single core Athlon64 at 4Ghz, that'd be a preferred choice over 2x2GHz for price and performance. Thus multicore has no limits in that you can keep increasing the number of cores, whereas single core is limited to fabrication techniques and clockspeeds and offers a peak-performance bottleneck compared with multicore.

 

[Carl B]

I don't think we should focus too much on Cell here, though it's obvious the chip and architecture will be supported for some time to come by all three companies.

The agreement really is an agreement for process research applicable to any and all chips (and I was surprised to learn it's the first announed to aim for 32nm). We've read a lot recently of how global chip foundries are hard-pressed to expend the R&D necessary to keep up with Intel and Samsung, and I think this should be viewed more as a pooling of research dollars to that effect. I just wonder how IBM will juggle it's partners since they have a concurrent agreement with AMD right now for 45nm as well, and Toshiba is part of other 45nm process research alliances as well (including a side one with Sony).

As to Cell though, I wouldn't imagine any current architecture gets tossed, but maybe expanded. As mentioned maybe the full DP support IBM is after, larger LS, support for a 'glueless' environment beyond two chips, XDR-2 (and beyond), multi-core (insert Kutaragi's roadmap here), etc etc...

Unless the boat gets seriously rocked, I'm expecting PS4 to have a Cell configuration completely B/C with the current, and another joint chip w/NVidia for some of the same reasons, that one likely as exotic as we would have originally liked.

 

[Titanio]

I don't think we should focus too much on Cell here, though it's obvious the chip and architecture will be supported for some time to come by all three companies.

The agreement really is an agreement for process research applicable to any and all chips (and I was surprised to learn it's the first announed to aim for 32nm).

It's actually not. In fact I think AMD and IBM have an agreement covering down to 22nm. And Intel has said they hope to have chips on 32nm by around 2009 (which is in line with this agreement's timescale - it's apparently 2005-2010).

 

[Carl B]

It's actually not. In fact I think AMD and IBM have an agreement covering down to 22nm. And Intel has said they hope to have chips on 32nm by around 2009 (which is in line with this agreement's timescale - it's apparently 2005-2010).

Yeah I actually knew the Intel 32nm plan, but didn't know about the IBM/AMD 22nm agreement. (which makes me wonder again how these concurrent research pacts are juggled)

I was really just referencing this BusinessWeek quote:

"This is the first public commitment by anybody in the world to 32-nanometer technology," says Richard Doherty, director of the market research firm Envisioneering Group.

 

[Titanio]

Yeah I actually knew the Intel 32nm plan, but didn't know about the IBM/AMD 22nm agreement. (which makes me wonder again how these concurrent research pacts are juggled)

Here's a link re. IBM/AMD:

http://www.cdrinfo.com/Sections/News/Details.aspx?NewsId=15423

Speaking of keeping your options open, look at Toshiba :

http://www.eet.com/news/latest/showArticle.jhtml?articleID=175803771

Japan’s Toshiba is said to be involved in other chip ventures; the company could be hedging its bets.

For example, seeking to regain lost ground in ICs, Hitachi, Renesas and Toshiba are expected to be among the first companies to form the long-awaited foundry fab venture in Japan, according to a report.

To complicate matters, NEC Electronics and Toshiba recently announced that the two companies would share the development of 45-nm CMOS logic manufacturing processes. In addition, starting with this joint development, the two companies have begun discussions on the possibility of a comprehensive alliance that would range from design and product development through to manufacturing.

Toshiba and Sony have been collaborating on process technologies up to 45-nm also. But a Toshiba spokesman didn't specify whether the companies would collaborate beyond 45-nm.

I presume each alliance and research work within each group focusses on different things..

 

[Carl B]

Toshiba's orgy of agreements I was aware of (and find their situation bizzarre), but the AMD agreement for 22nm must've flown right past me. I wonder how much AMD contributes (research-wise) to these AMD/IBM efforts incidently? It usually seems to me as if AMD pays IBM some money, and then gets pulled along by them in terms of process research. I could very well be underestimating their research contributions though. Either way, I dig my Athlons.

 

[Megadrive1988]

so this almost confirms that PS4 will be on a chip-process no larger than 32nm ?

 

[Carl B]

so this almost confirms that PS4 will be on a chip-process no larger than 32nm ?

That's a pretty good way of looking at it, didn't think of that. But PS3 was targeting 65nm a couple of years ago before they realized they'd have to ship at 90nm, so still possible we might see PS4 at 45nm.