Some quotes about PS3 CPU

[PC-Engine]

DC > PS3

 

[Farid]

DC > PS3

C'mon, it'll have 8 of thoses cells, so PS3 Cell will have a blazing 8 Gflops peak performance, though being a multi core CPU!!!

And if Kutaragi Ken's GS 3 have bilinear filtering, and dot 3 BM (in 2 passes, of course), and maybe mip mapping...

Hence, with luck, PS3 will might be almost as powerfull as Xbox!!

 

[m1nd_x]

this information can't be right.. maybe they meant "teraflop"., but, then that'd be insane.. so, umm.. i'm just going to wait till i see real news to comment..

 

[cthellis42]

I think the sarcasm dripping from this thread has burnt a hole out of my brain.

 

[McFly]

Sarcasm? Where?

Fredi

 

[cthellis42]

Sarcasm? Where?

^^^^^^^^^^ Right there! ^^^^^^^^^^

You just missed it!

 

[hovz]

how many gflops do the current top end processors and gpus have?

 

[McFly]

how many gflops do the current top end processors and gpus have?

Nvidia flops or real flops?

Fredi

 

[hovz]

actual ones, not the exaggerated manufactures claims. id be curious about the r3xx and nv3x series too

 

[Shinjisan]

I think that slide explains the concept of a cellular architecture in the Deep Blu case.It's not the Sony-IBM-Toshiba Cell
As far as we know the single Cell ia rated at 25 Gigaflops.
Which means that PS3 won't break the 256Gigaflops barrier easily or not?

 

[Brimstone]

I think that slide explains the concept of a cellular architecture in the Deep Blu case.It's not the Sony-IBM-Toshiba Cell
As far as we know the single Cell ia rated at 25 Gigaflops.
Which means that PS3 won't break the 256Gigaflops barrier easily or not?

Many people make the falacious mistake of comparing old style architectures to CELL. The design approach to CELL is very different from CPU architectures from Intel, AMD, and Power PC from IBM.

Just like the doubts about the clock speed being high are totally wrong. CELL is being built differently, so when they manufacture CELL they won't run into the same type of problems that hamper old-style CPU architectures.

A great example is MIT's raw where you have a processor designed to combat the problems of wire delay.

Our research addresses a key technological problem for microprocessor architects: How to leverage growing quantities of chip resources even as wire delays become substantial. The Raw research prototype uses a scalable instruction set architecture (ISA) to attack the emerging wire-delay problem by providing a parallel, software interface to the gate, wire, and pin resources of the chip. An architecture that has direct, first-class analogs to all of these physical resources will ultimately let programmers achieve the maximum amount of performance

Technology trends

Until recently, the abstraction of a wire as an instantaneous connection between transistors has shaped assumptions and architectural designs. In an interesting twist, just as the clock frequency of processors has risen exponentially over the years, the fraction of the chip that is reachable by a signal in a single clock cycle has decreased exponentially. Thus, the idealized wire abstraction is becoming less and less representative of reality. Architects now need to explicitly account for wire delay in their designs. Today, it takes on the order of two clock cycles for a signal to travel from edge-to-edge (roughly fifteen mm) of a 2-GHz processor die. Processor manufacturers have strived to maintain high clock rates in spite of the increased impact of wire delay.

...

We sized each tile so that the time for a signal to travel through a small amount of logic and across the tile is one clock cycle. Future Raw processors will have hundreds or perhaps thousands of tiles. The tiles interconnect using four 32-bit full-duplex on-chip networks, consisting of
over 12,500 wires, as Figure 1 shows. Two net-works are static (routes specified at compile time) and two are dynamic (routes specified at
runtime). Each tile only connects to its four neighbors. Every wire is registered at the input to its destination tile. This means that the
length of the longest wire in the system is no greater than the length or width of a tile. This property ensures high clock speeds, and the
continued scalability of the architecture.

THE RAW MICROPROCESSOR:A COMPUTATIONAL FABRIC FOR SOFTWARE CIRCUITS AND GENERAL-PURPOSE PROGRAMS

 

[Fafalada]

As far as we know the single Cell ia rated at 25 Gigaflops.

Ok that one I haven't heard yet before, where does this rating come from?

Which means that PS3 won't break the 256Gigaflops barrier easily or not?

Well, people bitched and moaned about Xenon leaked specs being underwhelming and THOSE broke 256GFlops 'easily' (by roughly 50%).

 

[nAo]

Ok that one I haven't heard yet before, where does this rating come from?

IMHO from nowhere..

Well, people bitched and moaned about Xenon leaked specs being underwhelming and THOSE broke 256GFlops 'easily' (by roughly 50%).

Ehehe..Xenon faster than PS3...

 

[MfA]

Oh come now, the Xenon leaked specs would correspond to something around 80 GFLOPS peak for the CPU.

 

[nAo]

Oh come now, the Xenon leaked specs would correspond to something around 80 GFLOPS peak for the CPU.

Well..maybe it will be faster (on the CPU side..) than PS3 for real..

 

[Fafalada]

Oh come now, the Xenon leaked specs would correspond to something around 80 GFLOPS peak for the CPU.

who said anything about the CPU?

Which means that PS3 won't break the 256Gigaflops barrier

Xenon system specs on that diagram were around 340GFlops. And that's for programmable rating alone. Should PS3 indeed end up being something silly like a software renderer, you'd end up spending programmable flops for crap like scan conversion...

Anyway, who knows, maybe PS3 will indeed be slower?

 

[bbot]

Does an 8-cell chip that runs at 1.16Mhz, that has a total computing power of 9.2Gflops, sound weak to you? Compared to the combined power of the vu's of the Emotion Engine of about 2Gflops, it's a definite improvement. That's assuming the engineering sample is an 8-cell chip, with each cell capable of 1.16Gflop.

 

[McFly]

This thread makes me sick and tyred.

Fredi

 

[Shinjisan]

I've read the 25Gigaflops quote right in this forum when a few Cell patents were being discussed People were hinting at a 3,6GHZ running part with a PowerPC core and 8 Vector units (what a single Cell should be).
Anyway the first Cell based workstations should be unveiled soon and PS3 specs themselves will be known in a 5 months time.
It will be interesting to see if and in what kind of Cell based product Sony can deliver on the Teraflop promise.
Personally a would be very disappointed with a PS3 not reaching 512Gigaflops globally.

 

[jvd]

I've read the 25Gigaflops quote right in this forum when a few Cell patents were being discussed People were hinting at a 3,6GHZ running part with a PowerPC core and 8 Vector units (what a single Cell should be).

i doubt we will see a 3.6 ghz cell being used in the ps3 , we'd see 3.6 ghz chips in the xenon before that happens .

A complex chip like cell is not going to scale that high nor was it meant to