Semiconductors from idea to product

[Rys]

I had a go at writing something that outlines the basic processes between starting idea and final chip mass production in modern consumer semiconductors, for the technology-minded lay person. Published at TR rather than here because TR.

http://techreport.com/review/28126/semiconductors-from-idea-to-product

If you've ever wondered what the basic steps are, it's hopefully mostly all in there

 

[aaronspink]

I had a go at writing something that outlines the basic processes between starting idea and final chip mass production in modern consumer semiconductors, for the technology-minded lay person. Published at TR rather than here because TR.

http://techreport.com/review/28126/semiconductors-from-idea-to-product

If you've ever wondered what the basic steps are, it's hopefully mostly all in there

Couple of things...

Why certainly digital tapes were once used to transmit designs, if you go back further, making photo masks was an actual real thing that was done quite literally manually with using effectively tape... Think sheets of plastic with tape on top and photo reduction to actual masks...

Also the exposure step of manufacturing doesn't actually etch the dies. The wafer is coated with a photoresist, put into the lithography machine, exposed, and then the non-reacted photoresist is washed away. Then the wafer is etched in chemicals (generally hydrofloric acid), then the reacted photoresist is removed. This is continuously repeated for each lithographic stage. There are also other stages of processing such as deposition, implantation, and oxidization.

Deposition is how you get things like metal layers on a die. In the old days this was done largely though sputtering(think of electrifying metal with high currents until it vaporizes) in vacuum chambers. These days they use Chemical Vapor Deposition which is much easier to control and gives more even thickness distributions.

Implantation is used to dope various base materials so that they exhibit different properties. Its basically how you get things like P nodes in an N wafer or N nodes in a P wafer.

Oxidization is how you grow things like a SOX boundary or barrier on a wafer.

For metal layers, the general recipe is, Deposition->Lithography->Etch->wash->Barrier Dep/Ox and repeat. Depending on the generation of process there will be a one or more stages of CMP (chemical metal polishing/planarization). For more advanced metal layers, this process can actually be repeated multiple times.

Also you left out wafer scale testing before dicing. Wafer scale test basically can figure out if there are gross wafer defects and do partial testing of the individual dies before dicing is done. Also in the case of external packaging, the fab generally ships with uncut wafers or cut but undiced wafers. Dealing with diced die is a major pain and is a step that is minimized as much as possible. So actual dicing almost always happens as part of packaging.

 

[Rys]

Nice, I didn't realise that masks were actually made with tape way back when. I really only understand the basics of how modern lithography works, thanks for the extra detail. I'll see if I can work that in to an update.

Does wafer scale testing always happen in modern production? I thought that kind of "is the chip operational enough for proper testing" didn't happen before dicing these days, because working with cut dice was reasonably straightforward and not too expensive now (mostly robotised, etc).

 

[aaronspink]

Nice, I didn't realise that masks were actually made with tape way back when. I really only understand the basics of how modern lithography works, thanks for the extra detail. I'll see if I can work that in to an update.

Does wafer scale testing always happen in modern production? I thought that kind of "is the chip operational enough for proper testing" didn't happen before dicing these days, because working with cut dice was reasonably straightforward and not too expensive now (mostly robotised, etc).

Well, real tape tape outs were quite a while ago. We aren't talking about high levels of integration for them. 10's to 100's of devices.

AFAIK, yes, wafer scale testing still happens, at least it did back 3 years ago. In general, it mainly more of a parametric test than a detailed functional test but is useful for the fab and can be coordinated with things like binning. But it can also be used to black out dies that likely won't make it which can save considerably on package and test (aka out of spec parametrics, etc).

 

[silent_guy]

Nice, I didn't realise that masks were actually made with tape way back when. I really only understand the basics of how modern lithography works, thanks for the extra detail. I'll see if I can work that in to an update.

My Really Old colleagues talk about reserving a large room and crawling from one part of the die to the next. When the silicon came back and there were bugs, they didn't even need to look at the schematic (not RTL of course) to know where to put the needle to probe.

Which is another thing that I haven't seen the 0.35um days (where it was already very tricky): ultra thin needles that you used to scratch the top oxide away and then place right onto a top metal layer and attach to a scope...

 

[Rys]

My Really Old colleagues talk about reserving a large room and crawling from one part of the die to the next. When the silicon came back and there were bugs, they didn't even need to look at the schematic (not RTL of course) to know where to put the needle to probe.

Which is another thing that I haven't seen the 0.35um days (where it was already very tricky): ultra thin needles that you used to scratch the top oxide away and then place right onto a top metal layer and attach to a scope...

I think the current state of the art for in-silicon analysis on modern technology is FIB to create the probe spots and then optical probes (or maybe a SEM, I'm not 100% sure) for the sampling. I wish I was around back when the techniques only needed human finesse, rather than machines, to have a go at it myself.

 

[silent_guy]

I think the current state of the art for in-silicon analysis on modern technology is FIB to create the probe spots and then optical probes (or maybe a SEM, I'm not 100% sure) for the sampling. I wish I was around back when the techniques only needed human finesse, rather than machines, to have a go at it myself.

Yeah, some of the current probing techniques are nothing short of magic, but you need specialists to operate it. Doesn't have the charm of dialing a knob back and forth to scratch away that piece of glass between your needle and the signal you want to observe.

At some point, we even patched a chip that way: a bunch of needles on the silicon, scratch a way a piece of metal completely to break the wire, then put some (minor) external logic, and feed it back into the chip.

That was soon replaced by FIB wires, which were a royal pain to get right, with very low yield. It would take hours to FIB a single chip, you'd patch 10, and if you were lucky, one would work. That doesn't really happen anymore as well: with 3 metal layers, you have easy access to all signals. With 10 not so much...

 

[aaronspink]

I think the current state of the art for in-silicon analysis on modern technology is FIB to create the probe spots and then optical probes (or maybe a SEM, I'm not 100% sure) for the sampling. I wish I was around back when the techniques only needed human finesse, rather than machines, to have a go at it myself.

The state of the art machines are dual probe based with separate probes for SEM and FIB. So you can basically blast away layer by layer while imagining. In addition, you can use the FIB to fix logic as well by basically patching in unused cells or by cutting off inputs and tying them to GND/VDD. Its pretty incredible technology.

While FIB patching used to be very hit or miss, my impression is that these days they have it pretty much down. And they can still fib the 10 layer parts, just have to be super careful.

 

[Rys]

In all of the designs I get to work with, there's always purposeful surfacing of wires up to the upper bits of the stack just in case metal rework might need to be done, hedging the bet basically.