Well? You wanted an answear to this? Normally I don't answear bullshit but here it goes.
Don't expect TFlops on the playstation itself anytime soon.
It seems that these TFlops are intended to be available in
distributed game servers
Again, this is both confirmed WRONG by IBM, Kutaragi, Okamoto, Cell patent.
Cell is an architecture, and is talked up by SCEI as a chip. Go look at their 200 billion yen investement, they clearly mention "microprocessor"
Now look what's being said about Cell?
Cell will be designed to deliver "teraflops" of processing power.
http://www.ibm.com/news/2001/03/12.phtml
My friend showed me his July 2003 issue of EGM and it has an entire page on ps3.
Here is what it says, this is from GDC 2002.
"Okamoto said the console would be capable of 1 trillion floating-point operations per second"
July EGM.
Now it's kutaragi's turn to take the bong hit.
One CELL has a capacity to have 1TFLOPS performance
Oh and last we have the Cell patent, or should I say PS3 patent. We see a chip design that has a capable max floating point power of around 1-1.5TFLOPS. This is Broadband Engine with the attached Rasterizer.
So let me see, Cell's TFLOPS performance is going to come when you have thousands of them hooked up over the net? I don't think so; not only does Hans de vries prove to not know what he is talking about. What he has said has been proven to be false by several people(and a patent) within the Cell development circle.
Lastly, SCEI and Toshiba are mass producing "Cell" on 65 nm. Why 65 nm if Cell is going to just be a chip where you will need hundreds to reach a 1TFLOPS performance? Why would SCEI take such a huge risk at 65 nm when 90 or dare I say even 130, both of which are proven processes would suit this lower chip fine?
But wait... A broadband engine type chip would be near imposible to put on 90 nm because of the heat would just melt the inside of your playstation. But waiiit... we have it being mass produced on 65 nm which would suit such a chip just fine, hell you even have Toshiba stating they will rush down to 45 nm ASAP.
But nahhh Toshiba and SCEI are simply just taking a huge risk and putting a few simple PPC cores on a chip at 65 nm because they want bragging rights because they will have a 65 nm chip before everyone else</sarcasm>