R420 on .11?

[Ardrid]

The Inq's got some more goodies for you guys and it's not Fudo this time. Charlie and Paul tend to be on point most of the time, so what do you guys think?

http://www.theinquirer.net/?article=15638

 

[hoom]

oooOOOOoooOoo
Maybe 600mhz wasn't so unlikely after all 8)

 

[dizietsma]

If it is true then that has been a well hidden secret , almost perfectly hidden except for 5 days or so.

Maybe that is why the confidence is high from ATi.

Or maybe it is the type of process and not the size of process that allows it to use lower power

 

[Ardrid]

I would say a little bit of both. I'm wondering about yields, as Charlie alluded to. .11 is extremely untested and it could spell disaster if it doesn't go right.

 

[Dave Baumann]

1.) 110nm is just a cost optimised optical shrink of 130nm, so a transisor on a 110nm die has the same properties as a transistor on 130nm

2.) Being optimised for cost, there are no low-k options for TSMC's 110nm process.

 

[loekf2]

0.11 um ? they went to a process shrink immediately ? this is a change to what they did with the 9700/9800 if i'm not mistaken. there they did the high-end part in 0.15 um and the mainstream part in 0.13 um.

not sure if 0.11 really means less power, okay less dissipation/gate, but on the other hand leakage goes up and they increased the clock.

PS: 0.11 is what you call a process shrink in the semiconductors industry. it usually means you design with a larger process in mind (= 0.13 um) and shrink the design optically in the fab. so, contrary to going to a different process node (e.g. 90 nm) you can stick to existing design tools etc. usually is easier (and faster) to do.

 

[Evildeus]

Does that mean that they could do it in 0.13 + low k? Or that the yield was pretty bad, contrary to a common belief? That sound interesting anyway 8)

 

[QuadPump]

that is nuts if it can actually go that low :S its usually nvidia who do bold moves like that..and it usually costs them big time

 

[Doomtrooper]

I think with all the leaks there isn't going to be much of a surprise...if everything is accurate of course

 

[bloodbob]

1.) 110nm is just a cost optimised optical shrink of 130nm, so a transisor on a 110nm die has the same properties as a transistor on 130nm

I some how rather doubt the properties of the two transistors are the same. Anyone who is in ASIC developement feel free to tell me I'm right and dave is wrong. Espically in such a complex part as the R420 and I dunno how analog circuits fair being optically shrunk ( I really dunno they might not give damn ).

 

[Doomtrooper]

http://www.xbitlabs.com/news/video/display/20030929004713.html

 

[loekf2]

1.) 110nm is just a cost optimised optical shrink of 130nm, so a transisor on a 110nm die has the same properties as a transistor on 130nm

I some how rather doubt the properties of the two transistors are the same. Anyone who is in ASIC developement feel free to tell me I'm right and dave is wrong. Espically in such a complex part as the R420 and I dunno how analog circuits fair being optically shrunk ( I really dunno they might not give damn ).

As I'm working in the semi business, normally it's just a geometry shrink (so in X and Y by some factor) meaning the properties of the standard cells and transistors remain the same. Nonetheless normally fabs do some tweaks in the diffusion (so what's before doing the metal layers) which are different from the original no-shrink process.

Yes analog can be shrunken as well. If... the design is prepared....

Personally I think it's a bold move to go 0.11 already. However, quite smar. From what I hear Nvidia's NV40 is a 300 mm2 (????) design, which sounds horrible to me ... looking at yields and costs. Even more if they plan to sell the same die in three or four configurations.

 

[bloodbob]

Well I'm out of my depth I guess I'll have to take your word for it.

 

[GeLeTo]

Transition to 0.11 micron technology will probably start in the second half of 2004... Hence, all next-generation ATI’s VPUs will be made using 0.13 micron technology, while the future generation graphics products, such as code-named ATI R500, will be manufactured using 0.11 micron technology. It is also possible that ATI will make a less complex graphics processor for mainstream or value market segment using 0.11 micron technology for evaluation the process in the second half 2004.

As I read it - R500 will be on 0.11, R420 will be 0.13 and some budget chip (most likely based on R3xx - i.e. not next-gen) will be 0.11

 

[Mariner]

Aren't we expecting 0.13 low-k for the R420 with a RV3X0 on 0.11?

I'm assuming here that 0.13 low-k is preferable to 0.11 in power consumption etc despite the smaller size?

 

[bloodbob]

Actually if it really is fesible to shrink the dies easily then something we could see is the R480 could be done on .11 after all ati did mention it would be more then just a refresh .

 

[hoom]

We do not have any problems with 0.13 margins. Actually, it is the opposite. We want to go into 0.13 and 0.11 very aggressively

Thats the important bit I think.
Wow so surprising & exciting!

 

[Dave Baumann]

Actually if it really is fesible to shrink the dies easily then something we could see is the R480 could be done on .11 after all ati did mention it would be more then just a refresh .

All going from 130nm to 110nm buys you is a smaller die size, hence lower costs. Without a low-k option its not likely to gain any performance, in fact you would probably loose performance if you were on 130nm low-k. I'm not sure there would be any point for high end ASIC's, unless you weren't using low-k in the first place.

 

[Tim Murray]

After .13u, the next process that uses low-k is .09u, correct?

 

[anaqer]

Here's some .11u for you:
( Although the PCB seems rather busy for a budget part, no? )