PS4 to use Cell, NOT PS3?

[Panajev2001a]

V3 you are correct... I thought it didn't give me figure for the SRAM, but it does ( we can assume 4-6 trasistors per SRAM cell [although it would be cool if they used 1-T SRAM by MoSys, of which they have the license, hehe bigger than regular DRAM cells, but smaller the SRAM... I guess it would not clock as high as the SRAM based Local Storage and that would be a problem... )...

I will correct the calculations...

 

[Panajev2001a]

Corrected version...

Very rough estimates ahead

Ok... so our budget is 350 mm^2

Ok... according to prof. Nair's research at IBM with 70 nm technology you should be able to embed 4.03 Gbits/cm^2.

64 MB = 0.5 Gbits which is 1/8th of 4.03 Gbits.

So we would need 1/8th of 1 cm^2 and this means:

1 cm^2 = ( 100 mm^2 ) / ( 8 ) = 12.5 mm^2

I originally also took the fugures for 100 nm, but that it is a bit too much considering their new process is 65 nm [and they seem pretty happy about DRAM cell's size and not 70 nm and that should also take into account the wide busses for the e-DRAM )...

350 - 12.5 = 337.5 mm^2

Now... basically the Broadband Engine has 32 APUs, 4 PUs ( very tight and compact cores ) + 4 DMAC and 4 MB of Local Storage ( LOS, SRAM based )...

Edit: each APU has 128 KB of Local Storage... I am just summing it up all together to simplify the discussion...

IBM's paper predicts around 577 MTransistors/cm^2 with 70 nm for SRAM... We can upgrade it to 600 MTransistors/cm^2 as they are using 65 nm technology.

4 MB ( total amount of SRAM based Local Storage ) = 32 Mbits = 0.03125 Gbits = 192 MTransistors. ( using 6 Transistors per bit )

( 600 / 192 ) = 3.125

1 cm^2 = ( ( 100 mm^2 ) / ( 3.125 ) ) = 32 mm^2

We have 32 Local Storages, each 128 KB, so we can assume that each Local Storage takes 32 / 32 = 1 mm^2

Let's assume the 4 PUs + 4 DMACs take all together 12 mm^2...

337.5 - 12 = 325.5 mm^2

We have 32 APUs...

This would leave:

(325.5 / 32 ) = ~10.1 mm^2 for each APU.

If we thought about the e-DRAM taking 30 mm^2 as the Nair paper suggested, regarding 100 nm technology, then we would have: ~9.6 mm^2 for each APU.

So, according to the "good scenario"...

10.1 - 1 = 9.1 mm^2 for the 4 FP Units and the 4 Integer Units and the thirty-two 128 bits registers.

According to the "bad scenario"...

9.6 - 1 = 8.6 mm^2 for the 4 FP Units and the 4 Integer Units and the thirty-two 128 bits registers.

VU0+VU1 in 250 nm take 70 mm^2 and we know VU1 is bigger than VU0 ( 2x the micro-memory, 1 more FMAC and one more FDIV )... so let's assume that VU1 measures around 40-44 mm^2.

Using 65 nm technology we should be able to shrink it to less than 10.35-11.44 mm^2 ( considerably less, assuming that redesigning the layout of the chip [in the shrinking process] would allow better die area usage optimizations... and that the SRAM cells in the Local Storage might be smaller than the SRAM cell used in the VU's micro-memories ) and that includes 32 KB of SRAM ( micro-memories ) and thirty-two 128 bits registers and sixteen 16 bits GPRs...

 

[Gubbi]

ARGH!

Motherfucking session-timeout

Gubbi...

From prof. Nair research paper on IBM's web site:

 Technology 	 	  nm 	180 	130 	100 	70 	50
  Gate length 	 	  nm 	140 	85–90 	65 	45 	30–32
  Density 	  DRAM 	  Gb/cm2 	0.27 	0.71 	1.63 	4.03 	9.94

I'm fairly confident that this DRAM density is for a dedicated DRAM process (stacked capacitor) and not a logic process (trench capacitor).

This guide lists eDRAM density as 230Mb/100mm^2 for a density optimized and ~110Mb/100mm^2 for performance optimized eDRAM in IBM's cu-08 process (0.13um). Even if SONY's CELL design doesn't feature full blown performance optimized eDRAM, it probably is fairly aggressive (to feed 1TFLOPS worth of FPUs), so density will be between 3 and 7 times worse than what is listed in the chart.

However, I don't see die size as the problem at all.

The sole problem is getting power consumption down to something that doesn't take a fridge to cool.

Cheers
Gubbi

PS. I had a longer response written up, but I apparently used so much time writing/reading that my session timed out, and had to log in again and then it was ALL GONE.

 

[Vince]

I'm fairly confident that this DRAM density is for a dedicated DRAM process (stacked capacitor) and not a logic process (trench capacitor).

This[/url] guide lists eDRAM density as 230Mb/100mm^2 for a density optimized and ~110Mb/100mm^2 for performance optimized eDRAM in IBM's cu-08 process (0.13um). Even if SONY's CELL design doesn't feature full blown performance optimized eDRAM, it probably is fairly aggressive (to feed 1TFLOPS worth of FPUs), so density will be between 3 and 7 times worse than what is listed in the chart.

Gubbi - if your numbers are for 130nm... um. The diffrence between 65nm and 130nm geometrically is massive! Does anyone knows the %?

SCE used a stacked capacitor on the GS, but has shifted to a deep-trench capacitor DRAM that they codeveloped with Toshiba. EETimes had a great article on this you should look for..

The basic press release from Toshiba said this:

Fabricated with 193-nm lithography and phase-shift masks, the transistor is reported to hit switching speeds of 0.72 picosecond for an n-MOSFET and 1.41 ps for a p-MOSFET at 0.85 volt. The embedded DRAM cell measures 0.11 micron2, allowing a 256-Mbit DRAM to be housed on-chip with logic. The process' embedded SRAM has a cell size of 0.6 micron2.

The new technology enables a 180-nm pitch, a 75 percent shrink from the 90-nm generation. The process employs a low-k dielectric material with a targeted effective interlayer dielectric constant of around 2.7.

Low-K, SOI... we'll see.

 

[Panajev2001a]

Gubbi.. if that happens just hit back on the browser... it works... I do that all the time

Thanks for the answer Gubbi... I am glad people read my posts and check my numbers ( thanks to Vince too )

 

[Panajev2001a]

Fabricated with 193-nm lithography and phase-shift masks, the transistor is reported to hit switching speeds of 0.72 picosecond for an n-MOSFET and 1.41 ps for a p-MOSFET at 0.85 volt. The embedded DRAM cell measures 0.11 micron2, allowing a 256-Mbit DRAM to be housed on-chip with logic. The process' embedded SRAM has a cell size of 0.6 micron2.

The new technology enables a 180-nm pitch, a 75 percent shrink from the 90-nm generation. The process employs a low-k dielectric material with a targeted effective interlayer dielectric constant of around 2.7.

Duh... I forgot about that PR...

I will recalculate the die size...

 

[Panajev2001a]

Ouch... it seems I was a bit off... 56 mm^2 for 512 Mbits ( 64 MB )and 28 mm^2 for 256 Mbits ( 32 MB )... maybe they are going with only 32 MB of e-DRAM in the Broadband Engine and 32 MB of e-DRAM in the Visualizer ?

I have to check how much mm^2 that would leave for the APUs...

 

[Gubbi]

Gubbi - if your numbers are for 130nm... um. The diffrence between 65nm and 130nm geometrically is massive! Does anyone knows the %?

I know. Which is why I only deduced a ratio of 3 to 7 times worse density for eDRAM over a dedicated DRAM process.

But 512Mb should still be well small enough at the 0.065um node, -somewhere in between my initial 120mm^2 estimate and Panajev's 12mm^2 (ie. around 40-60mm^2)

Cheers
Gubbi

 

[Panajev2001a]

Well... then the Sony and Toshiba numbers do work... let's see if I can do some quick approximation...

DRAM cell = 0.11 um^2

SRAM cell = 0.6 um^2

512 Mbits * 0.11 um^2 = 56.32 mm^2 ( rough estimate )

350 - 56.32 = 293.68 mm^2

We said 12 mm^2 for 4 PUs+4 DMACs

294 - 12 = 281.68 mm^2

4 MB = 32 Mbits * 0.6 um^2 = 19.2 mm^2

We have tirthy-two 128 KB Local Storages:

19.2 / 32 = 0.6 mm^2

We have 32 APUs:

282 / 32 = ~8.8 mm^2 for each APU

8.8 - 0.6 = 8.2 mm^2 for each APU ( excluded the 0.6 mm^2 Local Storage which is SRAM based ).

 

[Gubbi]

I believe the APUs will be alot smaller than that. But then I also believe that SONY is aiming for a die size well below 200mm^2. 350 mm^2 is Itanium 2 class ~ $1000/die.

The entire FPU in the new Opteron (0.13um) is just under 6mm^2. That is with 2 32bit FADD, 2 32bit FMUL, renaming logic and *alot* of registers (Athlon had 88 80 bit physical registers, I don't know if SSE is somehow mapped onto these).

Anyway, each APU will probably be super simple, -somthing like a dual issue in-order CPU core (one load/store and one ALU/FPU instruction per cycle). So it's size will probably be a little more than twice that of the Atlon FPU.

I'm guessing around 15mm^2 in 0.13um. With a 5-6 density increase going from 0.13 -> 0.065um that'll be around 2-2.5mm^2 or 75mm^2 in total for all 32 APUs.

I still don't think they'll run @ 4GHz though.
Guestimating is fun....

Cheers
Gubbi

 

[jvd]

I believe the APUs will be alot smaller than that. But then I also believe that SONY is aiming for a die size well below 200mm^2. 350 mm^2 is Itanium 2 class ~ $1000/die

Don't they charge more for the itanium do to valaditions for it to run in more than one chip config ?

 

[Gubbi]

Or perhaps because the large cache version has significantly higher performance (20%).

I don't think the cost of the die is much above $150, if at all. That is still alot of money spent on one chip going into a $250 piece of equipment.

Cheers
Gubbi

 

[Panajev2001a]

Gubbi... the APU are designed for 32 GFLOPS and 32 GOPS... at 4 GHz ( lowering the speed means that you have to increase the FP ops/cycle rating ) this means 8 FP ops/cycle obtainable from 4 parallel FMACs doing something like 4 parallel SIMD FP MADDs ( each is 2 FP ops/cycle )...

We have 4 FP Unis and 4 Integer Units in each APU plus 32 128 bits registers, other logic for instruction isse etc.. and the 128 KB of Local Storage SRAM based...


Thank you though for helping guess-estimate ,
Goffredo


P.S.:
I am not trying to shoot numbers left and right though, this is not a joke

 

[Panajev2001a]

PlayStation 3 should not cost less than $299 ( maybe a bit more, maybe not ) with internal launch cost for each unit to be closer to >$350 or even $400 ( or a bit higher if they were selling PlayStation 2 at $380 with losses... it is also true that they bhad bad yelds of the GS at taht time and shortages )

No wonder why they are pushing hard to get 45 nm in the plants as soon as they can ( they seem to really want to transition from 65 nm to 45 nm as soon as they can ) and that should say something about things like chips' size and all...

Also, 350 mm^2 is big... but we are also talking about 300 mm wafers... I hope they can fit it on less than that and I am just trying to understand if they can now...

The EE and GS were well above 220 mm^2 in 250 nm ( due to shortages in several PlayStation 2 destined for the Japanese launch had 250 nm GS chips )...

The 250 nm GS was 279 mm^2 and the 180 nm EE was 224 mm^2 with the 250 nm EE being 240 mm^2

Before I wanted to see if the yelds of 350 mm^2 chips on 300 mm wafers ( initial maximum of 25,000 wafers a month, but I used 15,000 to be more conservative ) would have been enough to satisfy launch demand and now I am trying to guess-estimate the chip's actual size based on the patent description...

What would be your estimate for the PU RISC cores ?

 

[Paul]

I expect PS3 to be 300 bucks not 250.

Ok let's say ps3's CPU does infact cost 150 dollars each to make(for the record EE costed 100)

PS2 launched in japan at a cost of about 380 USD. Sony was obviously losing money on each system sold regardless, so you had the cpu at 100 dollars, then let's say the rest of the system costed 250-300 dollars more. Total price for making a ps2 im guessing was around 400 dollars im guessing.

Now for ps3, sony can get away selling it for 400 in Japan, so 150 for the CPU and then let's say 300 for the rest. So it's around 450 bucks.

Then for the USA launch the price of the things will go down and they will get it to sell for 300 for us. Although they will shit on some of the components a bit like they did for ps2, (it's why american system's get DRE's and Japan's dont)

 

[jvd]

I expect PS3 to be 300 bucks not 250.

Ok let's say ps3's CPU does infact cost 150 dollars each to make(for the record EE costed 100)

PS2 launched in japan at a cost of about 380 USD. Sony was obviously losing money on each system sold regardless, so you had the cpu at 100 dollars, then let's say the rest of the system costed 250-300 dollars more. Total price for making a ps2 im guessing was around 400 dollars im guessing.

Now for ps3, sony can get away selling it for 400 in Japan, so 150 for the CPU and then let's say 300 for the rest. So it's around 450 bucks.

Then for the USA launch the price of the things will go down and they will get it to sell for 300 for us. Although they will shit on some of the components a bit like they did for ps2, (it's why american system's get DRE's and Japan's dont)

Depends on how much ram they put in it . How much a blue ray player costs . Also if they are including a hardrive and a modem or ethernet card. If xbox 2 launches before the ps3 and includes a hardrive and a modem there is no excuse to not launch with them . There was no excuse for sony to not lunch with the ps2 without a modem either .

 

[Panajev2001a]

Why... ? the price for online games is the same...

With PlayStation 2 you need a Broadband Adapter and with the Xbox you need the Xbox LIVE starters kit...

 

[Paul]

Depends on how much ram they put in it . How much a blue ray player costs . Also if they are including a hardrive and a modem or ethernet card. If xbox 2 launches before the ps3 and includes a hardrive and a modem there is no excuse to not launch with them . There was no excuse for sony to not lunch with the ps2 without a modem either .

The 300 dollars for the rest of the system covered all that. Remember, they are making the parts not buying them from a store. The parts will cost WAY less each to make. And Sony will once again be taking a hit on each unit sold also.

 

[jvd]

Depends on how much ram they put in it . How much a blue ray player costs . Also if they are including a hardrive and a modem or ethernet card. If xbox 2 launches before the ps3 and includes a hardrive and a modem there is no excuse to not launch with them . There was no excuse for sony to not lunch with the ps2 without a modem either .

The 300 dollars for the rest of the system covered all that. Remember, they are making the parts not buying them from a store. The parts will cost WAY less each to make. And Sony will once again be taking a hit on each unit sold also.

I agree with just one thing . Ram will be bought (rambus most likely) and the blueray player will be very expensive as it seems this will most likely be the first thing it is in

 

[jvd]

Why... ? the price for online games is the same...

With PlayStation 2 you need a Broadband Adapter and with the Xbox you need the Xbox LIVE starters kit...

With the dc i didn't need anything .

Seems u agree with the hardrive part though .