Predict: The Next Generation Console Tech

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7 + 5 = 12 = 6 + 6
12 = 16 - 4

7 - 1 SB= 6 out
5 - 1 SB = 4 in

Theoretically:
6 out = 24 Gb/sec
4 in = 16 Gb/sec

So you agree that the FlexIO bus consists of a number of directed 8 bit channels? I honestly have no idea of what your previous angry rant was all about and I don´t care.
 
It can't, but neither can the RSX memory controller. It's more of a constraint of the RSX command processor to service address requests from Cell...
 
It can't, but neither can the RSX memory controller. It's more of a constraint of the RSX command processor to service address requests from Cell...

I understand that Cell can instruct RSX to perform reads on its behalf and transmit the data to XDR via DMA, and that this is how everyone does it if they need to do it.

With a measly 16MB/s, though, I wonder why they made it possible at all to support direct VRAM reads by Cell, then? Something necessary for bootstrapping? PS3 doesn't support cache coherency protocols between the VRAM and Cell, surely..
 
Crossbar said:
Yes it´s not even 0.5% of one channel
Well as nAo points out - this is provided strictly as debug-path, not "oh this is the best we could do with limitations of FlexIO and/or RSX"-path.

The fact that the reasoning behind "oh you'll never need to readback from GPU except for debugging" is dumb is another matter, but this isn't exactly the first time hw engineering side missed the point(especially on Sony hardware).
 
Well as nAo points out - this is provided strictly as debug-path, not "oh this is the best we could do with limitations of FlexIO and/or RSX"-path.

The fact that the reasoning behind "oh you'll never need to readback from GPU except for debugging" is dumb is another matter, but this isn't exactly the first time hw engineering side missed the point(especially on Sony hardware).

Yes, but it is the first time they miss the point while going on record for years (Hofstee did it several times) about "proper" two way communication between CPU and GPU thanks to the system architecture they were planning.

Yes, that was IBM talking about that over and over (well, Hofstee was), but Sony did get it right with PSP and although it required a bus reversal process you could read e-DRAM at a faster speed than 16 MB/s...

Is nVIDIA to blame for this? ... dunno...
 
I take it you mean PS2 - bus reversal there was an example of not getting it right, and again it was largely a debug feature, running at less then half of actual bus speed (still, it was 30x faster then on PS3).
If PS2 had a bi-directional bus to GS, deferred shading could have been standard practice for the past 8 years already. Nothing else really compares in terms of unrealized potential, and ironically it's the least known of 'missing' features on any of the consoles.

PSP missed the point elsewhere, but I let it slide because as a handheld it's been ahead of its time anyway.
 
Nothing else really compares in terms of unrealized potential, and ironically it's the least known of 'missing' features on any of the consoles.

Do most software developers not know about how to use it and are just not requesting it of the console hardware companies ? Or is it "simply" a hardware cost-cut?
 
I don't see Larrabee being very effective in graphics with less than 32 core, which is the middle ground, given that Larrabee can have as few as 16-24 (even 8 for lowend products) and as many as 48-64.

I would imagine that IF Sony does select Larrabee, it would be a 2nd-gen Larrabee which is apparently already in development (LRB2), and use 32 or 48 or 64 cores (not 16 and probably not 24), on a 22nm process, in 2012. We can assume Sony will launch PS4 by no later than 2013, but more likely 2012 give that Microsoft will probably launch in 2011-2012.

Larrabee might be better suited to the next-gen Xbox than PS4, since Sony does not really need Larrabee since they have CELL and Nvidia. Microsoft might want to have a manycore CPU/GPU/GPGPU. Although Microsoft probably has more options: i.e. create their own CPU as reported in 2006, or go with a next-gen multicore or manycore Xenon-like IBM PowerPC based CPU, paired with the next-next gen AMD/ATI GPU (R900 or better).
 
I take it you mean PS2 - bus reversal there was an example of not getting it right, and again it was largely a debug feature, running at less then half of actual bus speed (still, it was 30x faster then on PS3).

I worded it badly, I meant:

PSP --> example of getting it right (well at least under several aspects... VFPU, logical UMA, etc... about what they got wrong... it happens with handhelds and engineers' egos ;)).

and

PS2's GIF-to-GS bus reversal --> at least it could be reversed and read at more than such a worthless speed although yes it was not quite fast enough...
 
I take it you mean PS2 - bus reversal there was an example of not getting it right, and again it was largely a debug feature, running at less then half of actual bus speed (still, it was 30x faster then on PS3).
If PS2 had a bi-directional bus to GS, deferred shading could have been standard practice for the past 8 years already. Nothing else really compares in terms of unrealized potential, and ironically it's the least known of 'missing' features on any of the consoles.

I remember this 'missing feature' used to be pointed out during DC Vs PS2. Then DC died and so was this 'missing feature'.
 
So what new forms of FSAA can be used in the future ? I know that ati has a new mode that uses the shaders to perform fsaa. Is there anyhting else out there ?
 
So what new forms of FSAA can be used in the future ? I know that ati has a new mode that uses the shaders to perform fsaa. Is there anyhting else out there ?

CSAA seems fitting, but maybe the IQ benefits at 1080p after just plain 4xMSAA aren't worth even the (relatively) small cost associated with it -- of course being the IQ whore that I am I feel it is worth it, but I'm not making these decisions :neutral:. Still we'll want something that takes care of more than just polygon edges.

There's good discussion of some creative solutions in this thread.
 
Just to word to point out that whoever get the larrabee (if any) might very well be able to launch @22nm.
In fact I like more and more the idea of Sony going that route (a clean start and pass on BC) and put his development muscles at work on what could really well be a beast.
 
Well this article is pretty much a sum up of this thread but some part are imho off. For example the writter acknowledge that Ms may be more conservative in regard to hardware cost but he think about:
a 128GB SSD which would cost 50$ at launch
a gpu as big as the xenos
2 controlers both pretty advanced (batteries included, better radio transmission, advanced motion sensing, etc.)
Edram => more silicon + a more expansive motherboard
I think he considered power consumption and thermal disspation to lightly and he is not alone, we've been overlooking (including me) comments of more knowledgeable members in this regard.
For example the 40nm process from TSMC is rumored to be pretty bad, it has been an eye opner for me. Basically ATI and Nvidia will be limitated not by die sizes this time around but by power consumption. High end GPU have already pretty much hit the roof with ~300watt they have very little legs in this regard, new TMSC process may bring very little in this regard. We may not see a jump in the transistor budget (or frequency) for the generation of gpu made on this process, no neat jump in power if anything tinier/cheaper chips.
How will be 32nm? could be good or bad... But if a console were to launch this year @40nm its gpu for example would have to be significantly less powerfull than a HD48xx which burn 300watts.

That's clearly a point in favor to larrabee no matter its efficiency in graphic department at least we know that Intel 45nm and likely 32nm process are/will be good. Shortly Intel may pack in significantly more transistors than its competitors.
The foundry company (if it actually turn to exist) has at least AMD 45nm process looks pretty good,may be they will need to keep some foundry busy? :)
Back to larrabee I think that the news about the bad TMSC 40nm process is clearly a good sent for Intel. By fall 2009 they might very well be able to launch a larrabee that significantly bigger than its competitor that extra raw power could very well be a pain in the ass for both ATI and Nvidia (even if software/side side is likely to suck), at least gpgpu is more and more of a given for Intel. With 32nm likely to be here by 2010... both ATI and Nvidia have some work on the table I guess.
 
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For example the 40nm process from TSMC is rumored to be pretty bad, it has been an eye opner for me. Basically ATI and Nvidia will be limitated not by die sizes this time around but by power consumption. High end GPU have already pretty much hit the roof with ~300watt they have very little legs in this regard, new TMSC process may bring very little in this regard. We may not see a jump in the transistor budget (or frequency) for the generation of gpu made on this process, no neat jump in power if anything tinier/cheaper chips.

I suspect ATI and Nvidia are both looking at other foundries that don't have the same problems or switching to 32nm sooner (assuming TSMC have that done right).

It's getting so mind bogglingly expensive to develop processes now (est at $3bn) it must be only a matter of time now before TSMC join the IBM club.

I wonder how long even Intel can keep going it alone. There will come a point that developing their own process will cost more than any advantage it gives them.
 
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