PowerVR Series 5 to debut in 2003 using 0.13u

[Joe DeFuria]

Don't flatter yourself, Teasy. I'm not following you around. I make more posts on this board than just "Teasy and PowerVR related" you know.
Lighten up, dude.

BTW when I said more likely DX9.1, I only meant higher then DX9....

Right. So you say it's "most likely" to be "higher than DX9." For the record, and I think it most likely will not be higher than DX9.

So......Care to wager?

In any case (wager or not), what are you basing your speculation on? I don't see much in the way of PowerVR product history or market drive to suggest that they ever release new hardware based on the latest brand new API. (Which is what 'higher than DX9' would be next year.)

 

[arjan de lumens]

With a decent memory subsystem (128-bit DDR2 would count as "decent") a well-designed tiler should be able to push 100+ million polys per second before binning becomes the bottleneck - this should be enough to handle even scenes dominated by HOSes and displacement mapping at a decent frame rate.

The way I see it, the best way for IMG to get rid of the perception that tilers are bottlenecked with the binning issue would be to announce actual support for N-patches+displacement mapping. This would indicate at least faith that their architecture is ready for the heavy-duty polygon pushing that will follow. If they don't support it, well .. too bad.

Also, if they are going for the high end, they need to implement some sort of Multisampling as well - which I expect should be rather easy in a tiler?

 

[Grall]

Joe:

Why do you assume it won't be higher than DX9 if it's (supposedly) scheduled to come out around third or fourth month of 2003? We got higher than DX9 ALREADY man!


*G*

 

[Humus]

The Kyro series cards were a little behind in features ... so if history means anything ...
Not saying that it can't be a full DX9 part though.

 

[Ty]

The Kyro series cards were a little behind in features ... so if history means anything ...
Not saying that it can't be a full DX9 part though.

Actually I think the Kyro I was quite decent feature-wise (other than TnL) but II was certainly getting long in the tooth and the SE was really just a waste of time unfortunately.

The portion of the quote that scares me is always the way they refer to classifications of products. That in itself would be fine except for the fact that they always seem to shoot for the mediocre range. Everyone keeps on saying (for years now) how tilers are so wonderful that I keep on hoping for a product that will just knock my socks off.

Till then I guess my 9700Pro will just have to do though.

 

[Ailuros]

The Kyro series cards were a little behind in features ... so if history means anything ...
Not saying that it can't be a full DX9 part though.

As you're implying that's hardly an indication for anything.

If this is as serious as it looks, then coming closer next year to release I'll just sit back and laugh at the speculations and back and forth arguments, that are most probably going to fly around the net.

Hasn't the Inquirer picked up something already? LOL

I don't care who's fault it was in the past that execution suffered so badly, but that's actually the biggest and foremost concern I have with ImgTec. For that I'll rather wait to see the future licencee getting announced, if and when there will be one.

Considering that they need 13um to fit in whatever they want to and the estimates one could make on clockspeeds, number of pipelines etc. for me personally anything above dx8.1 will be completely sufficient. I couldn't care less about stuff that will get into real use months if not years past release.

Anyway from what I have been able to gather they don't plan to play softball this time around, but that doesn't change my above standpoints one bit.

 

[LeStoffer]

I don't care who's fault it was in the past that execution suffered so badly, but that's actually the biggest and foremost concern I have with ImgTec. For that I'll rather wait to see the future licencee getting announced, if and when there will be one.

Yeah I share this concern and would like to add the simple point that it will take quite a lot of effort to cut a market share out of nVidia and ATI as things stand now. Things are just going damn fast, while ImgTec's chips seems to evolve to slowly to really keep the market they might have captured initially.

Another point: While the PowerVR architecture removes the burden of rendering useless (hidden) pixels, it doesn't change the fact that we are going in a direction of being less constrained by mem. bandwidth and more constrained by lack of computational shader power IMO.

I once were very excited by the PowerVR design, but today I need to be conveinced all over again.

 

[Nagorak]

I think the major selling point of Power VR breaking (breaking the bandwidth barrier) has basically been destroyed thanks to DDR memory and now faster and faster DDR memory. They developed a system for defeating a bottleneck that never developed thanks to faster memory, along with some HSR aspects incorporated in IMRs. The deferred rendering approach might actually be "better" and maybe the one to choose if one was able to choose which path 3D graphics initially followed. It is a smarter approach...

But now that IMRs are the standard and faster memory has made memory bandwidth less of a concern, there's just not enough going for Power VR anymore. I'll give them this: they have one more shot at breaking into the market. If this next chip does not compete favorably with ATi and Nvidia's chips, then that's it: game over.

In that case Nvidia and ATi will just keep pumping out IMRs until memory speed seriously becomes a problem and then promptly switch over to deferred rendering long after Power VR is out of the picture.

 

[Dave Baumann]

IMHO it would help when IMG would explain binning and binning space to the users too ( I suppose You do this with developers already to lessen the reservation against TBR's there ). IMHO this would help IMG to overcome the impression that TBR have an big problem with high polygon-counts and the storage of polygons for binning. Without this explanation You will receive a lot of reservation when You introduce the next chip. See old threads in this forum for more info.

Personally I think the best thing to do right now is just demonstrate it. People can continuously bleat on about this being an ‘issue’ but if they can’t actually demonstrate where it might become an issue then they don’t really have anything to stand on.

Why do you assume it won't be higher than DX9 if it's (supposedly) scheduled to come out around third or fourth month of 2003? We got higher than DX9 ALREADY man!

I think the important thing to note here is that the part is being designed now. Specs for series 4 were floating around the web two years before it was supposed to be available. The reason we haven't seen a part based on contemporary API functionality is the length of time it took at get the licensee up and running.

From the EETimes article: “As well as class-leading functionality….He said that it was not yet decided whether Imagination would get first silicon implementations or test chips made at a licensee's wafer fab or at a foundry wafer fab in Taiwan." To me that would sound like they are basing that on the API for the period they they have finished their development, the key for time to market is how long it will take to get a licensee sorted out. However, given the last statement if they haven’t got one it sounds as though they may even go as far so produce the first silicon themselves for once.

But now that IMRs are the standard and faster memory has made memory bandwidth less of a concern, there's just not enough going for Power VR anymore. I'll give them this: they have one more shot at breaking into the market. If this next chip does not compete favorably with ATi and Nvidia's chips, then that's it: game over.

With long shaders coming along its not all going to be about bandwidth though is it? Its about how long its going to take to produce each pixel. IMR’s Z rejection schemes are cutting down the amount of occluded pixel being rendered, but so far they are have far from a 100% hit ratio, which is something that TBR can guarantee.

 

[LeStoffer]

IMR’s Z rejection schemes are cutting down the amount of occluded pixel being rendered, but so far they are have far from a 100% hit ratio, which is something that TBR can guarantee.

Okay, no one can argue about that of course, and we don't even have a consensus on how efficient the GF3/4, R8500 or R9700 are on random (e.g. not front to back) sorting. I would, however, assume that game developers would start to sort front to back more often (if they can) since so many cards (architectures) today are built to take advantage of it. (Both ATI and nVidia are asking developers to do it etc).

 

[Ailuros]

I have a hard time believing that either ATI or NVIDIA will eventually switch to a TBR architecture as long as they have alternatives. Not only would the switch cost too much, but with the cut-throat intervall both release products in all segments I doubt they could deal with the problems that could surface in no time.

Irrelevant to wether PowerVR have failed in the recent past to have all industry standard features in their products, it still doesn't mean that one should overlook their years long experience dealing with defered rendering. Granted both ATI and NV hold patents on TBR, so what? Can anyone even confirm that either or is doing any effective research with TBR? It doesn't have to be the PC space necessarily, console would be an option then too.

As for wether a Tiler would still hold advantages to the day or not a very simple example would include anything that includes on chip computational tasks and in extension anything antialiasing.

 

[JohnH]

There's a patent explaining how PVR works when it runs out of binning space, I haven't got a link handy, Simon could probably point you at it. One thing thing that is often forgotten when talking about binning space requirements is the triangle fill/rasterisation rules that OGL and D3D specify. Basically if you take these into account it becomes obvious that the ratio of binning space to poly count is non linear, almost logarithmic in fact. Add a bit of compression, and for any true "real time" graphics binning space isn't really an issue, not that it matters as in the cases where it does there's a solution.

When it comes to features, you can either take JohnM's statement at face value, or debate it, your choice. Nuff said.

John.

 

[Ailuros]

LeStoffer,

From my very limited knowledge/understanding I doubt that developers can completely avoid back to front sorting.

 

[Humus]

For translucent stuff you need to sort back to front, but that's a rather small part of the whole scene normally.

 

[Nagorak]

LeStoffer,

From my very limited knowledge/understanding I doubt that developers can completely avoid back to front sorting.

I guess back to front is the worst case scenario for IMRs (even with Z-rejection since nothing would be rejected). Do deferred renderers like Power VR do better at these though? If so it appears they still do have a major advantage.

I'll be the first to say that I'll happily jump on the TBR bandwagon and buy a Power VR card if they can come out with something that performs well, with good features and a decent price (and no serious problems)... Guess we'll just have to wait and see.

 

[Ailuros]

I recall at least the KYRO having almost identical scores between front to back, back to front and random order sorting.

I don't think KYRO had any "serious" problems either, but since Series5 seems to be far more advanced and thus more complex, I'd rather wait and see.

I've personally waited for a high end Tiler for a long time. Here's to hope that they'll execute and release on time.

 

[Joe DeFuria]

Why do you assume it won't be higher than DX9 if it's (supposedly) scheduled to come out around third or fourth month of 2003? We got higher than DX9 ALREADY man!

That's simple:

1) There's no gurantee that by the 3rd or fourth month of 2003, that there MS is even scheduling to release something higher than DX9. Seems to me that MS is building "legs" into this release of DX. And MS has never released a new API faster than "one year at a time" anyway.

2) IMG Tech have always designed not for bleeding edge, but for market mainstream. DX9 has a good chance of being more of a "mainstream" part by this time next year, but certainly not anything higher than DX9, and definitely not by Q1 / Q2 of next year.

In short, IMG TECH is going to have to drastically change it's usual design goals if they are going to be releasing a part "beyond DX9" by Q1 / Q2 of next year.

Not saying it can't happen of course. Could it be a DX9 part? Possibly. (Though likely, I don't think that's for certain either. ) I really don't see much of a chance of it being beyond DX9 though.

EDIT: BTW...did I miss something, or where did was the "3rd or 4th month of 2003" ever mentioned as a target release date? After skimming the article again, all I found was "2003"...

 

[Ailuros]

Joe,

Apart from the usual pissing contests you two have a habit to have, can you give me a reasonable explanation (yes considering their past track record) what on earth they need 0.13um for?

As a Tiler it does not only upon default need less transistors than an IMR, but they could go for even a 4 pipe/15um/dx9 compliant budget sollution.

Don't take that single bet this time around, you're going to loose it

edit:

In short, IMG TECH is going to have to drastically change it's usual design goals if they are going to be releasing a part "beyond DX9" by Q1 / Q2 of next year.

As you said yourself no one said anything about exact timespan of release; but what exactly would keep ImgTec from having a drastical change in the supposed usual design goals?

For the record apart from the fact that I almost had two birthdays until the Neon250 finally made it to the market, do you mind comparing it's featureset with that of a V2 at the time?

 

[Dave Baumann]

The Inquirer[/url]]Metcalfe said Imagination would be using the “same architecture as all alongâ€￾ which he understood to be superior to Trident’s offering which he reckoned was just tiling for memory rather tiling a full scene.

He said Imagination expects to produce products of "class leading performance" next year but refused to be more precise regarding the date.

So, now we have "class leading" Performance and Functionality quotes. Whether they will or won't be by the time its released is another matter, but this doesn't sounds like the traditionally conservative line we've heard before.

 

[Mariner]

To me, the most obvious benefit to the consumer of a capable DX9 Tiler would be the reduced pricing. Assuming PVR manage to get a chip out which is on time, stable and competitive in performance to those of ATI/NVidia, i would, in theory at least be much cheaper.
In the past, the transistor count of PVR chips has been much less than for IMR chips. If this continues to be the case then the chips should be much cheaper.
Additionally, it is likely that the performance of a tiler with a 128-bit memory interface could be equivalent to that of a 256-bit IMR. The pin count of the chip would be much lower further reducing cost.
Finally, a tiler might be able to get away with using less 'exotic' memory speeds i.e. instead of top-of-the-line DDRII, it may be able to use slower clocked DDR which would also be cheaper.
Lots of 'ifs' here, but I'd love to see ImgTch finally bring something to market at the right time!