PowerVR Series 5 to debut in 2003 using 0.13u

[Simon F]

Oh and Teasy and Joe... can you make the bet a bit interesting... some extra motivation for the teams here is always a nice bonus

Hmmmm....how about this. If Teasy wins, then I won't post a naked picture of myself.

We utterly refuse to give in to threats of torture.

 

[Ailuros]

You don't have to. Just get a bunch of Scotsmen and make them lift their kilts in front of Joe; should be enough to counter him

 

[megadrive0088]

In all seriousness, I would not expect PS & VS 3.0 standards to arrive until NV40 in 2004, or at the very soonest, in R400 at the end of next year. of course it would also depend on the timing of DX10 would it not?

 

[PC-Engine]

Since ray tracing can be realized relatively cheaply on a TBR, would we see it first from a PowerVR chip? Series 7, 8, 9?

 

[KimB]

In all seriousness, I would not expect PS & VS 3.0 standards to arrive until NV40 in 2004, or at the very soonest, in R400 at the end of next year. of course it would also depend on the timing of DX10 would it not?

Speaking of which, I wonder if ATI will attempt to continue their 12-month new architecture cycle that they've had since the original Radeon? Conversely, I wonder if nVidia will attempt to accelerate their own cycles?

Personally, I think that ATI will have to slow down, sooner or later, due to manufacturing constraints. It makes more sense to introduce a new architecture when a new process is available...

 

[Joe DeFuria]

It makes more sense to introduce a new architecture when a new process is available...

That depends on your engineering talent. Is it easier to introduce a new architecture when a new process is available (giving you a larger transistor budget)? Yes. nVidia seems to go this route.

However, ATI have yet to release a product on any 0.13 process, let alone a fully matrue one. I see no reason why ATI can't continue to create a new core every 12 months or so.

Assuming new processes are available about every 18 months (as per roughly Moore's law), this means that ATI can design a new core on a new immature process, and then 12 months later, design a "significantly" different core for the same, but more mature process.

Similar to what they did with the R-200 and R-300. Both on 0.15. The latter being much more advanced.

That being said, IMO, the thing that's going to dictate the "frequency" of significant new cores is going to be more related to the frequency of new DirectX releases. And I have a feeling that they may be slowing down....

 

[KimB]

That depends on your engineering talent. Is it easier to introduce a new architecture when a new process is available (giving you a larger transistor budget)? Yes. nVidia seems to go this route.

However, ATI have yet to release a product on any 0.13 process, let alone a fully matrue one. I see no reason why ATI can't continue to create a new core every 12 months or so.

Don't forget that nVidia once went in a similar direction, back with the original TNT. They haven't made such a change in die size as was made from the TNT->TNT2 since, and I have a feeling it's because they learned something from that experience, and it most likely has to do with money. (the die size change in the GeForce architecture was much smaller, and there has been no die size change in the GeForce3 architecture).

As for how "easy" it is to use a more advanced process, I don't think it's easier in any way, shape, or form. Beyond the increase in transistor counts, every die shrink brings along with it more problems with things such as noise and tunelling, meaning things that might have worked great at, say, .18 micron may not work well at all at .13 micron.

That being said, IMO, the thing that's going to dictate the "frequency" of significant new cores is going to be more related to the frequency of new DirectX releases. And I have a feeling that they may be slowing down....

I don't believe that for one moment. I feel very confident that it's the hardware manufacturers that are driving the releases of DirectX.

Still, it does beg the question as to why DX9 was not released along with the Radeon 9700. It could be due to a number of factors, but I think a big one was that ATI wasn't ready. As a point of evidence, they've only very recently released the specs for exposing the new pixel shader features in OpenGL (Is that extension available in drivers yet?).

 

[FUDie]

It could be due to a number of factors, but I think a big one was that ATI wasn't ready.

Careful, your bias is showing. If ATi weren't ready, why is their hardware here NOW? Maybe you're confusing ATi with some other IHV?

As a point of evidence, they've only very recently released the specs for exposing the new pixel shader features in OpenGL (Is that extension available in drivers yet?).

D3D != OpenGL. In fact, this comparison is ludicrous.

 

[Snap]

As a point of evidence, they've only very recently released the specs for exposing the new pixel shader features in OpenGL (Is that extension available in drivers yet?).

Errrm, I actually think that's because they were doing the responcible thing and waiting for the ARB Vertex & Fragment program extensions to be ratified so they would support them rather than separate extensions. I've not yet heard of them releasing specific instructions 9700.

 

[Joe DeFuria]

Don't forget that nVidia once went in a similar direction...(the die size change in the GeForce architecture was much smaller, and there has been no die size change in the GeForce3 architecture).

You missed my point. No, nVidia has never done what ATI did with R-300.

nVidia has done two things in the past, with respect to new cores and new processes:

1) They either introduce a new core (with significantly higher transistor count) on a mature process - which has resulted in lower than 'anticipated' clock rates. (Example: Riva 128 to TNT-1, TNT-2 to GeForce 256).

Or

2) They introduced a new core on a new process, thus 'maintaining' and possibly getting higher clockrates. GeForce2 Ultra to GeForce3, and GeForce3/4 to NV30.

nVidia has not to date ever done what ATI just did: Introduce a new core with significantly new complexity, on an old process, while maintaining / bumping up clock rates.

In other words, my basis for saying that ATI could in the future maintain it's "significant new core every 12 months", despite a new process not being available, is because they have just demonstrated that they don't 'need' a new process to churn out a very impressive part.

While nVidia has demonstrated that they will produce a new core on an old process, they have at the same time demonstrated that those particular products are not overly impressive. nVidia has historically 'needed' a new process to do that.

As for how "easy" it is to use a more advanced process, I don't think it's easier in any way,

Allow me to clarify. You face different issues when using a bleeding edge process, than you do trying to push the limits of a mature process. Neither route is easy. But from the standpoint of simple economics....with a given number of transistors, it's cheaper ("easier") to make the part on a more advanced process.

nVidia obviously thought it would be "easier" to make the NV30 on 0.13. (In fact...didn't their CEO say that 0.13 is really required for such an advanced part like the NV30? )

 

[ActionNews]

Hmmm....i haven't read the whole thread, so sorry if it's already mentioned:

1. Why do you all think PowerVR needs a licence? As i know John Metcalfe mentioned in the EE Times Interview, that PowerVR is thinking about producing Series5 themselfes !

2. In the EE Times Interview John Metcalfe said, that FSAA4Free and the Vertex Geometry Processor implemented in PowerVRs MBX is originally part of Series 4, so Serie 4 could have been a very interesting product ! And so why shouldn't PowerVR plan Serie 5 as a DX9-Part? As a DX8 kompliant chip it (IMHO) wouldn't have much advantages against Serie 4 and PowerVR doesn't need to develop Series 5.

But time will tell ...... !

CU ActionNews

 

[ParkLife]

That's not exactly what he said. You've taken specifics when none were given. In that article all the talk was intentionally kept as general, with a lot of 'coulds' and 'mights' type thing.

If you go back and read the article you'll see that you are presuming some things that certainly weren't said.

 

[ActionNews]

a little late, but.....

I haven't benn in this Forum for a long time, but what did i then misunderstand?

EE Times speaks about:

Metcalfe added that the Series-5 architecture would debut in 2003 in a 0.13-micron process technology. He said that it was not yet decided whether Imagination would get first silicon implementations or test chips made at a licensee's wafer fab or at a foundry wafer fab in Taiwan.

That sounds for me as PowerVR is thinking about producing their Serie 5 Chip directly "at a foundry wafer fab in Taiwan" without any licencee (at least testsamples.

And about FSAA4Free and Vertex Geometry Prozessor you can read:

At that time some technologies were pulled forward into the MBX cores, such as vertex geometry processing, and Series-5 architecture development was accelerated, he said.

Oh yes nothing about FSAA4Free...sorry. www.paraknowya.net (at the moment down )! said in a news message about that EE Times article, that FSAA4Free were part of Series 4, too. So at this point i have to correct me!

But there are other interessting things in the article:

Metcalfe said that Series-5 architecture would be based on a primary processing pipeline and a series of hardware accelerators that can be optionally switched in and out to render graphics.

"As well as class-leading functionality, there will be some unique features enabled by tile-based rendering," said Metcalfe.

So i think Serie 5 will be very interesting! Hopefully a DX9-Part .

CU ActionNews

 

[ParkLife]

Hopefully within a reasonable time frame!

 

[PC-Engine]

That sounds for me as PowerVR is thinking about producing their Serie 5 Chip directly "at a foundry wafer fab in Taiwan" without any licencee (at least testsamples.

All that means is that they haven't decided whether or not to use a fab in Taiwan or a fab owned by an existing PowerVR licensee such as NEC or STM etc.

 

[MfA]

The existing licensees have no license for the Series 5.

 

[PC-Engine]

The existing licensees have no license for the Series 5.

We don't know that for sure. Maybe there're negotiations happening right now..who's to say?

Anyway this quote means....

made at a licensee's wafer fab or at a foundry wafer fab in Taiwan

it will be made at a licensee's fab (whoever that may be) OR UMC, TSMC etc.

The former obviously means a fab owned by a licensee. Maybe it will be Intel who knows.

 

[MfA]

They had a list with the number of licenses in the AGM presentation, but that seems to have disappeared. Just because they say it might be made at a licensee fab does not say they have a licensee, which they almost certainly still dont. As far as we know Intel has only licensed MBX.

 

[Teasy]

All that means is that they haven't decided whether or not to use a fab in Taiwan or a fab owned by an existing PowerVR licensee such as NEC or STM etc.

Yes, which means they may produce early chips themselves. There basically saying that as of yet they don't know if they'll have a licencee before they start producing test samples.

BTW STM don't have there own fabs, they always used TSMC for Kyro 1/2 chips, also STM have left the market so they will not be involved.

 

[Ty]

BTW STM don't have there own fabs, they always used TSMC for Kyro 1/2 chips, also STM have left the market so they will not be involved.

STM doesn't have their own fabs? Just because they used TSMC for the Kyro line doesn't mean that STM lacks its own.