This is the relevant patent filed by AMD for mesh shaders:
https://patentimages.storage.googleapis.com/ef/96/c3/2e0b7028bbc378/US20200035017A1.pdf
This patent itself is dependent on another filing for fusing shaders:
https://patentimages.storage.googleapis.com/93/1b/29/41f6eb09923776/US10353591.pdf
The goals, as set out in the patents, are threefolds:
(1) Exploiting the inherent parallelism of GPUs
(2) Escaping the shackles of fixed function blocks in the pipeline, especially as it pertains to the vertex shader stage.
(3) Making use of only local data storage (caches & registers) by preventing round trips to main memory and thus gaining in latency and keeping bandwidth needs at a minimum.
Does the PS5 has something similar to this ? As I have said before, I do think that it does. There is a very interesting patent from Cerny about the use of compute shaders for index culling/compression prior to the verte shader stage:
https://patentimages.storage.googleapis.com/9a/e7/f0/80a69fa1d6553d/US10176621.pdf
Notably:
(1) The use of compute shaders exploit the SIMD nature of GPUs
(2) The implementation of a ring buffer that will store the outputs from the compute shaders to be read by the vertex shaders emphasizes the exclusive use of GPU caches to effect said culling. Very interestingly, this use of a ring buffer calls for synchronisation/coherency between the two shader stages as it relates to the eviction of data from the caches, something reminiscent of the GPU cache scrubbers mentioned by Cerny.