My description was vague, for someone that was not familiar with CPU/GPU intricacies... but you raised the interesting question of "what makes a core?"
My lowest-level definition is that "core" is a physically distinct path that an instruction stream's associated signals traverse between stages that reside in a generic Von Neumann or related architecture's memory.
This does still require at least one ALU, and at least one port to memory, but exclusivity for either is not absolutely necessary--although it gets iffy once this gets reduced to near-absurdity.
At a bare minimum, there would need to be a physically independent pipeline control unit, a mechanism for generating the program counter, and some physically independent context storage necessary for the the prior two elements to work through an instruction stream.
So, it's a physically separate pipeline control, and at least enough storage for a program counter.
The gray area, since I didn't require ALU exclusivity as an absolute, is if the necessary ALU for generating the PC were somehow shared between two cores. However, that would require an arrangement where an ALU is subject to two schedulers or pipeline control units that are still somehow physically distinct, and I haven't thought up an arrangement where that's workable.
Everything beyond that is increasingly negotiable in terms of sharing or necessity.
Decode? Could be shared, and for some defunct VLIW CPUs, not necessary.
FP? Could be shared, and CPUs predate that functionality.
Cache? Same.
A Von Neumann architecture, in its simplest theoretical implementation, makes no provision for interrupts. The preponderance of all cores in the world do service interrupts, but at least the possibility of a simple system that utilizes no interrupt signals is allowed for, as odd as that might be.
...and the fact that you cannot index them directly - that is, like a SPU (an embedded RISC processor would still be a full processor, even if you cut the outside access, but it is in principle there, at least).
The choice to hide direct indexing of the hardware is more of an API or platform issue. At least from the POV of the GPU's internal firmware, it can make the distinction.
The PS4 in particular may be allowing lower-level access for compute, although what that entails is not disclosed.
In the other direction, the increasing virtualization of execution resources or hardware-level sleight of hand makes it increasingly less likely that the cores software exist or are in use are what it actually gets.
An embedded RISC processor with no access to the outside, would still support interrupt and all the techs that are part of a processor. CUs do not (at least, yet).
Not yet, but the architecture has been drilling down to very few features out of a large list of attributes ascribed to cores.
I think it's close enough to consider them for the most part primitive cores, with some haziness when it comes the scheduling hardware that kicks in at the boundaries of kernel execution--which would include scheduling new contexts or someday potentially switching them.