PhyreEngine - New Hotness Sponsored by Sony? (moved)

[patsu]

Yes... accessing the Local Store is fast since it's on-die and there is zero cache logic. Need to look up my Cell book.

 

[liolio]

256 if I remember correctly

256MB/s, I guess right? It doesn't sound ok to me.
I had different values in mind, I though of something like say X is the size of the cache/LS line in bits, 3.2 the speed in GHz, say one SPU can "read" or "write" one cache/LS line per cycle, I expected the result to look like this:
X*3.2/8 (in GB/s)
If a cache/line is 128bits that's ~51GB/s for read and write operation.
If a cache/LS line is 256bits that's ~102GB/s for read and write operation

If a SPU can "read" and "write" a cache line per cycle the values for would be twice as high.

256MB/s seems low to me and I can't find maths that would lead to such "even" values, WTF?

 

[patsu]

I vaguely remember it's stated in # of clock cycles (to fetch a line).

EDIT: Your question reminded me that I may have misplaced my Cell book during the office move.
I shall find it tomorrow.

 

[Shifty Geezer]

256MB/s, I guess right? It doesn't sound ok to me.[/quotethat would be crippling.

Arwin will have meant 256 GB/s, and maybe have been thinking of the EIB.

I had different values in mind, I though of something like say X is the size of the cache/LS line in bits, 3.2 the speed in GHz, say one SPU can "read" or "write" one cache/LS line per cycle, I expected the result to look like this:

Exactly. I don't know the maths, but the BW is a nonsensical figure.

 

[patsu]

EIB bandwidth according to wiki:
http://en.wikipedia.org/wiki/Cell_(microprocessor)#Element_Interconnect_Bus_.28EIB.29

Bandwidth assessment

For the sake of quoting performance numbers, we will assume a Cell processor running at 3.2 GHz, the clock speed most often cited.

At this clock frequency each channel flows at a rate of 25.6 GB/s. Viewing the EIB in isolation from the system elements it connects, achieving twelve concurrent transactions at this flow rate works out to an abstract EIB bandwidth of 307.2 GB/s. Based on this view many IBM publications depict available EIB bandwidth as "greater than 300 GB/s". This number reflects the peak instantaneous EIB bandwidth scaled by processor frequency.[41]

However, other technical restrictions are involved in the arbitration mechanism for packets accepted onto the bus. The IBM Systems Performance group explains:

Each unit on the EIB can simultaneously send and receive 16B of data every bus cycle. The maximum data bandwidth of the entire EIB is limited by the maximum rate at which addresses are snooped across all units in the system, which is one per bus cycle. Since each snooped address request can potentially transfer up to 128B, the theoretical peak data bandwidth on the EIB at 3.2 GHz is 128Bx1.6 GHz = 204.8 GB/s.[33]

This quote apparently represents the full extent of IBM's public disclosure of this mechanism and its impact. The EIB arbitration unit, the snooping mechanism, and interrupt generation on segment or page translation faults are not well described in the documentation set as yet made public by IBM.[citation needed]

In practice effective EIB bandwidth can also be limited by the ring participants involved. While each of the nine processing cores can sustain 25.6 GB/s read and write concurrently, the memory interface controller (MIC) is tied to a pair of XDR memory channels permitting a maximum flow of 25.6 GB/s for reads and writes combined and the two IO controllers are documented as supporting a peak combined input speed of 25.6 GB/s and a peak combined output speed of 35 GB/s.

To add further to the confusion, some older publications cite EIB bandwidth assuming a 4 GHz system clock. This reference frame results in an instantaneous EIB bandwidth figure of 384 GB/s and an arbitration-limited bandwidth figure of 256 GB/s.

All things considered the theoretic 204.8 GB/s number most often cited is the best one to bear in mind. The IBM Systems Performance group has demonstrated SPU-centric data flows achieving 197 GB/s on a Cell processor running at 3.2 GHz so this number is a fair reflection on practice as well.[42]

I believe EIB is used to read another SPU's LocalStore, or other memories. Accessing your own LocalStore should be faster.


... and then I see this:

Optical interconnect
Sony is currently working on the development of an optical interconnection technology for use in the device-to-device or internal interface of various types of cell-based digital consumer electronics and game systems.

*Sigh* Project probably killed ?

 

[liolio]

So some stuffs are clearer now.
Cache line has to be 128bits.
And we have two cases to explain the figures total bandwidth is 51GB/s
So there are two cases:
The SPU can read or write one cache line per cycle =>51 GB/s
or
The SPU can read and write 2 cache lines every 2 cycles => 25.6GB/s +25.6 GB/s worth of bandwidth

 

[Shifty Geezer]

Why do you want this number? Are you interested in the bandwidths of any other processor's L2 caches or similar?

 

[liolio]

Why do you want this number? Are you interested in the bandwidths of any other processor's L2 caches or similar?

It's ok I got the overall figure, actuall I was thinking of another topic and how relevant it could be to do blending operations in LS.

 

[Arwin]

256MB/s, I guess right? It doesn't sound ok to me.
I had different values in mind, I though of something like say X is the size of the cache/LS line in bits, 3.2 the speed in GHz, say one SPU can "read" or "write" one cache/LS line per cycle, I expected the result to look like this:
X*3.2/8 (in GB/s)
If a cache/line is 128bits that's ~51GB/s for read and write operation.
If a cache/LS line is 256bits that's ~102GB/s for read and write operation

If a SPU can "read" and "write" a cache line per cycle the values for would be twice as high.

256MB/s seems low to me and I can't find maths that would lead to such "even" values, WTF?

I meant 256GB obviously, but I was wrong, it is 33.6GB for SPE code to access its own Local Store. Here's a really excellent overview:

http://books.google.nl/books?id=f9F...wBQ#v=onepage&q=local store bandwidth&f=false

 

[legendCNCD]

Sounds like something from Swoboda's demo presentation at Assembly or where it was

Yes http://www.youtube.com/watch?v=vQ2iQQvofCE

 

[Gitaroo]

wow, that looks nice, need new zone of the enders games....

 

[Titanio]

GDC 2011 PhyreEngine 3 slides:

http://research.scee.net/files/presentations/gdc2011/2011-GDC-PhyreEngine.pdf

 

[patsu]

PhyreEngine 3.5 Arrives Today for PS3, PS4, PS Vita
http://blog.us.playstation.com/2013...engine-3-5-arrives-today-for-ps3-ps4-ps-vita/

The latest version of this popular games development framework, PhyreEngine 3.5, is releasing to game developers and publishers worldwide right now! Today’s update builds upon the PS4 support introduced in previous versions. With PhyreEngine 3.5, PS4 developers will finally be able to leverage the platform’s advanced compute functionality, in addition to a host of other development-related features. Another convenient addition to PhyreEngine 3.5 is the ability for developers to make in-game edits on the fly and see their results immediately, without a lengthy wait for the changes to be recompiled.

Even if you’ve never heard of PhyreEngine, you’re probably familiar with some of the games that use its technology: Journey and RocketBirds: Hardboiled Chicken, just to name a few. PhyreEngine was initiated by Sony Computer Entertainment to streamline cross-platform game development between PS3, PS4, and PS Vita.

Bah... PhyreEngine was also used to make Demon's Souls and Dark Souls. ^_^

Would be way cooler if the end user can edit the levels like the developers.

 

[dagamer]

PhyreEngine 3.5 Arrives Today for PS3, PS4, PS Vita
http://blog.us.playstation.com/2013...engine-3-5-arrives-today-for-ps3-ps4-ps-vita/



Bah... PhyreEngine was also used to make Demon's Souls and Dark Souls. ^_^

Would be way cooler if the end user can edit the levels like the developers.

Or stick the game on the Vita. Instant sales!

 

[patsu]

You mean getting the Souls series on Vita ? I will be all over it.

Right now because of the locked save scheme, I can't play Dark Souls in the office if I had played it last night at home. The Cloud save feature will prevent me from copying the save to another machine within 24 hours since I last played it. I hate this 24 hour limit for locked saves. Have a second copy of Dark Souls at home, but I seldom play it because of this restriction.

If they have a Vita version, it would imply that I could sync the save to the Vita to play immediately, and then sync to the PS3 again.

 

[Wynix]

You mean getting the Souls series on Vita ? I will be all over it.

Right now because of the locked save scheme, I can't play Dark Souls in the office if I had played it last night at home. The Cloud save feature will prevent me from copying the save to another machine within 24 hours since I last played it. I hate this 24 hour limit for locked saves. Have a second copy of Dark Souls at home, but I seldom play it because of this restriction.

If they have a Vita version, it would imply that I could sync the save to the Vita to play immediately, and then sync to the PS3 again.

The director of demons and dark souls is not working on dark souls 2, that might be because sony have made a deal with FROM to get him to work on demons souls 2. *crossesfingers*