DeathKnight
Regular
Yeah man! I mean, they look so similar you can barely distinguish them apart!unlike MS , which comes up with a shrunk desktop
Yeah man! I mean, they look so similar you can barely distinguish them apart!unlike MS , which comes up with a shrunk desktop
Panajev2001a said:look at the motherboard pictures... and rotate 90 degrees the Desktop PC's picture...
vrecan said:who would want wireless controllers? I cant stand wireless everytime I am in a middle of a game bam the batteries go out... who wants to charge their console controllers?
I dont mind letting it charge overnight!who wants to charge their console controllers?
crystalcube said:vrecan said:who would want wireless controllers? I cant stand wireless everytime I am in a middle of a game bam the batteries go out... who wants to charge their console controllers?
I do and many other people too would like to have a wireless controller.
We are talking about something that is going to be released 2 - 3 years later and you think there will no progress in this area ?
It would be actually good if the capability is built into PS3 so if any controller goes down the system automatically pauses the game. If the controller can run continuosly for upto 6-8 hours on single charge that would really be ok for most of the people. For who play continuosly for 24+ hours theres the option of buying two of them so they can replace the controller while playing.
One controller to play one to charge ...and sony can sell more controllers this way too
It would be good if PS3 has some kind of generic wireless interface built into it like bluetooth maybe.
would it not be wiser to just buy different batteries depending on your desires? i mean a normal player would only need a battery that can last like 6-8 hours maximum. a more hardcore gamer would buy a (more expensive) battery that can last to up to, i don't know, 14 hours (who actually plays for 14 hours straight is beyond me)... and the batteries kinda go shitty after months, just like cellphones batteries, so u'd need to change batteries. no need to change the whole controller....
london-boy said:would it not be wiser to just buy different batteries depending on your desires? i mean a normal player would only need a battery that can last like 6-8 hours maximum. a more hardcore gamer would buy a (more expensive) battery that can last to up to, i don't know, 14 hours (who actually plays for 14 hours straight is beyond me)... and the batteries kinda go shitty after months, just like cellphones batteries, so u'd need to change batteries. no need to change the whole controller....
Yen's architects believe that memory latency, or the delay that results when a fast processor has to stop what it's doing to fetch data from a slow memory chip, is the main bottleneck in today's servers. Server processors have become like a Ferrari engine that runs at 150 mph but can't get enough gas to keep running.
To tackle this problem, Sun is designing chips that, when they debut in 2005, will have four processors that each handle four threads, or the subprograms that can be executed independently. This way, whenever a processor stalls because it has to fetch data, it moves from one thread to another.
``Memory has been falling behind for a long time,'' said Yen. ``Rather than fight it, we're learning to deal with it. It's a fundamental change of mind.''
It is a pity AMD isnt getting on board, x86-64 is probably a better instruction set for SMT than either Itanium with its huge register set or Sparc with its register windows.
Mfa... why is Itanium bad for SMT ( beside being an in-order issue and execute machine ? [except with LOADs/STOREs] ) due to the register file ?
The Alpha EV8 was supposed to have MANY more registers Itanium 2...
The EV8 is an 8 instruction issue wide out-of-order execution superscalar RISC processor that also supports 4 way simultaneous multithreading (SMT). The front end of the EV8 is a 64 KB, 2-way set associative pseudo dual ported instruction cache that supports the fetch of two separate 8 instruction cache lines each cycle. The EV8 branch predictor can predict up to two branches per cycle and the indices of the two instruction cache line fetched may be either sequential or disjoint depending on its decision. The two groups of 8 instructions are buffered (per thread) and merged in the "collapser", a functional block that chooses the 8 out of the 16 fetched instructions on the most likely path of execution, as predicted by the branch logic. These 8 instructions are register renamed and entered in a 128 entry out-of-order instruction issue queue. Each cycle, the queue selects up to eight data-ready entries for dispatch to the 8 integer units, 4 floating point units, 2 load units, and 2 store units that comprise the EV8’s execution resources [1]. As is customary, the issue queue selects the data-ready instructions that have been in the queue the longest. Unlike the EV6 instruction queues, the EV8’s design does not attempt to maintain program order of entries by shifting down instructions to fill vacant entries. Instead instructions are given an age vector when they enter the queue. The age vectors can be combined with a common "bid" vector using simple and fast logic to select the oldest data-ready instructions for issue. This new scheme allows out-of-order issue queues to be built with many more entries than previously possible, yet be capable of faster operation.
Unlike the EV6, the EV8 uses both a common instruction issue queue, and a common physical register file for both integer and FP operations. The EV8 supports 4 SMT thread contexts, each of which have 32 integer and 32 FP registers, for a combined total of 256 architected state general-purpose registers. In addition, the unified register file also contains 256 renaming registers, one for each of 256 possible instructions in flight, for a grand total of 512 registers. The EV8 needs 16 logical read ports and 8 logical write ports in its register file to support the sustained execution of eight instructions per cycle. A 24 port, 512 entry register file is not a nice thing to have sitting on a critical path so the EV8 designers resorted to the time honored solution of replication. The EV8 unified logical register file physically consists of two separate 512 entry, 8 read port and 8 write port physical register files. The overall total of 1024 64-bit registers in the EV8 is equivalent to the entire 8 KB data cache in the first Alpha processor, the EV4 (21064).