NVIDIA Kepler speculation thread

[H]...

 

Wonder what "canned benchmarks" are meant here.

 

http://75.126.99.220/showpost.php?p=1038448529&postcount=462

 

Looks like we now have Nvidia drivers for a Radeon board. 256 bit, GDDR5, Stacked DVI, +DP, +HDMI, 1536 shaders on a sweet spot chip, small bare die on substrate w/o IHS...probably will have multi-monitor support...where they get these ideas? I hope that digital mosfet / inductor + slaves are high-end too - that would be another smart idea. Wonder if this will have zero core power, flickering at 120hz and 157/300 idle clocks.

A super-powered 28nm Cayman board with NVCP + inspector! Don't care what the price is, this will sell out.

 

Not sure how I feel about those numbers. If the 680 is "GK110" based and 50% faster than a 580 that's a bit disappointing. We could probably get that from 28nm Fermi. If it's GK104 based then that's a bit too good to be true. It would put it a step above Tahiti giving nVidia a perf/mm and possible perf/w and perf/$ advantage.

 

Thanks, but that is still a bit cryptic. But at least it means it's no pure compute benchmark, where raw TFLOPs would matter the most.

 

Prolly 3DMark11 or Unigine or Stonegiant etc.

 

iirc roughly the density reduction from 40nm to 28nm is ~ 100% but the projected power reduction was in the ~ 40% range (from memory). Assuming power, and not density, is the current "wall" a 50% performance increase while keeping the same power seems like a reasonable expectation.

Disappointing? Maybe. But would not that disappointment properly be placed on the slowed pace of process technology? Unless NV has some really big architectural surprises in their hat I would say anything far above 50% performance gain at the same power draw would be amazing.

 

Next one in line...
GK107 wants to be measured: http://we.pcinlife.com/forum.php?mod=redirect&goto=findpost&ptid=1844549&pid=33452412

GT 650M: 384SPs@ probably 810MHz and 128-Bit 1,8Gbps DDR3

 

Hmm, I can't "lock" on any reference measure in this one. Anyone have the dimensions of those DDR3 chips?

 

Matches this from BSN a little over a month ago, except that the screenshot in BSN shows 96 CC and this one shows 384 CC. Assuming they're the same chip but one of the programs doesn't look at , does that mean each Kepler SM is 4x the size of a non-GF100/GF110 Fermi SM, that is, 192 CC?

That allows the "8 group" and "7 group" stuff from SemiAccurate to fit with the 1536 SP rumors, as 1536 = 8·192.

Also, can anyone figure out the die size from that photo?

 

Looks like 50% more performance over a 550M @ same 1.8Gbps DDR3 in the SM3.0 of 3DM06:
http://i51.tinypic.com/nq44li.jpg
http://www.cooltoyzph.com/viewitem.php?iid=632

 

gpu-z shows hotclocks...?

 

Probably. The GPU reports like a Fermi a GPU clock and a memory clock. On Fermi base clock was calculated by the GPU clock. But on Kepler you have just one clock.

 

So the one clock of this particular Kepler is 810 MHz and the 405 MHz "base clock" doesn't actually exist?

 

That would I guess.
Also 384SPs@405MHz should be to low to gain 50% more perfomance over 96SPs@1480MHz.

 

In other words those frequencies showed depends on gpuz that is not updated?

 

so gk104 is probably going to be called gtx680 then, right.

it kinda works out, 50% more raw shading power at the same base clock as 580, so if its clocked a bit higher 45-50% better perf in 3dmark seems possible.

 

How big will the jump from GK104 to the "big bad boy" then be? If "the small guy" is 50% faster than 580?

Guys, if that's correct, another GF 8800 times are coming. I suspect.

 

XDR2 to the rescue? *SCNR*

The Cayman/GF110 comparison tells me, you want to ride the clock speed train for memories. But how likely is it really that Nvidia is beating AMD wrt to memory clocks this round? I think about as likely as beating them with regard to transistor density.

And what about the possibility that the big guy's more optimized for HPC workloads, owing his bigness to big 52 bit multipliers (or two 32 bit multipliers and corresponding carrier networks) and according datapaths and register files throughout the chip?