NVIDIA GT200 Rumours & Speculation Thread

Discussion in 'Architecture and Products' started by Arun, Feb 10, 2008.

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  1. Rys

    Rys PowerVR
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    Confirmed by who, exactly? It can only really be one person, IMHO :razz:
     
  2. nAo

    nAo Nutella Nutellae
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    Well..10 processors confirmed (if the pic is not photoshopped..)
    [edit] wow you guys are fast..:)
     
  3. CJ

    CJ
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    It's photoshopped alright. To put my name in it. :wink:
     
  4. fellix

    fellix Hey, You!
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    Are those uniform blocks in each cluster caches or register arrays?!

    Looks like the I/O logic is not taking so much area, given the already huge overall die area.
     
  5. Rys

    Rys PowerVR
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    <modhat>
    I'm getting increasingly sick and tired of the polarised and off-topic streams of crap polluting this and the RV770 thread. People who should seriously know better are fueling fires that need not be fueled, using personal attacks they somehow think are OK to air here. It's not OK. Stop it now please. I shouldn't have had to say that, sorry to those contributing properly who this doesn't apply to *sigh*
    </modhat>
     
  6. Slyne

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    10? So there's no redundancy for GT280? I had so far assumed (16-1)x16 for that very reason.

    Well, maybe they have a smarter implementation of redundancy these days.
     
  7. leoneazzurro

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    ROPs? There are 32 of them, if I can count well.
     
  8. Jawed

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    I have to say I'm bemused that there are no clearly repeating L2s, ROPs and MCs to be seen. I wonder what's going on there?...

    The other thing that's really puzzling about this is there are lots of areas that "don't line up nicely". e.g. the borders of the clusters vary in size considerably and look kinda randomly placed.

    Jawed
     
  9. Domell

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    OK. I got it.
    BTW. Can you confirm any The inquirer rumours about GT200b@55nm?
     
  10. fellix

    fellix Hey, You!
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    Now I see that each cluster consists of three symmetrical parts (10*3 = 30 of something?). Could this be for the redundancy?
     
  11. CJ

    CJ
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    Check one of my earlier posts. ;)
     
  12. no-X

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    it's actually 8, not 10 (marginal-ones are half-sized)
     
  13. Slyne

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    In order to cut through the 5-8 coming pages of questions, opinions and answers regarding hard-to-describe, obscure regions of that pic, could anyone knowledgeable try and create a labeled version of it? (and I could even learn a thing or two in the process :grin:)
    Thanks
     
  14. fellix

    fellix Hey, You!
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    [​IMG]
     
  15. Arun

    Arun Unknown.
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    It's 10, 3x8 in each, no coarse redundancy. Anyway, since we're letting the cat out of the bag here... This is also based on a die shot, although a better one so if you can't corroborate it, you'll just have to believe me:
    ~26.5% SMs, ~26% Non-SM Clusters (TMUs etc.), ~14.25% memory I/O, ~13.25% unique, ~8% MCs, ~6.25% ROPs, ~2% Misc. I/O, 4%+ Misc. (intrachip I/O, rounding errors, unidentifiable units, etc.)
     
  16. ShaidarHaran

    ShaidarHaran hardware monkey
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    Man NV's ROPs are cheap... Yet so powerful! Why does ATi's approach suck so badly in comparison? Referring to Z/AA rates here, of course.
     
  17. Kaotik

    Kaotik Drunk Member
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    Do we know exactly what functions of the chip are over at the NVIO chip?
     
  18. nAo

    nAo Nutella Nutellae
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    Any more info on this big chunk?
     
  19. fellix

    fellix Hey, You!
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    Any guess for the cache size? There are vividly 48 (16*3) SRAM banks in each triplet.

    Damn -- at least double the resolution of the die shot would reveal much more. :shock:
     
  20. Jawed

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    What are you distinguishing here? Memory controllers and physical interfaces?

    So, overall, 8 channels of memory amount to 22.25% of the die?

    Jawed
     
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