NVIDIA GT200 Rumours & Speculation Thread

Both probably right - as soon as you run badly out of memory on the former cards.

 

Yes, 2x 9800GX2 would be in some cases < 2x 8800 Ultra (scroll down).

But the 7k in Vantage Extreme seemed to be a GTX 280 SLI or some people only misunderstood the "2x 9800GX2".

 

I was just checking Charlie Demerjian's news and comparing it to NDA info I have myself and I realized that although Charlie's interpretation is very anti-nVidia, some of it is right. So I'm inclined to believe Charlie knows GTX 200 specs and clocks, just his info about RV770 is way off, which is why he claims that single RV770 will be on par with the GTX 260.

 

And it has 3 times its floating point performance ? So, the missing mul maybe is still missing...

 

933GFLOPs / 384GFLOPs is only 2.4x and I would think/heard some times ago, modern code is more demanding MADD.

 

For what it's worth:

http://www.fudzilla.com/index.php?option=com_content&task=view&id=7604&Itemid=1

and: http://www.fudzilla.com/index.php?option=com_content&task=view&id=7603&Itemid=1

 

Nvidia GT200 sucessor tapes out

This doesn't look very good, maybe even disappointing:

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/Offtopic... I wish people would actually turn back a few pages to check if a link wasn't already posted.

 

What's the current blending rate ?

 

Thanks.

One thing that I'm a bit dubious about is the way that a cluster is split into multiprocessor and TMU. There are parts of a cluster that aren't either, as far as I can tell, relating to scheduling/instruction issue.

So I'm wondering if some of the area that's being counted as TMU is something else.

I'm curious about the batch size (number of elements in a hardware thread) on GT200. G80 has an underlying batch size of 16 but I have the impression that it'll be 32 in GT200. I wonder if this leads to some simplification of the multiprocessors, or at least in the scoreboarding/scheduling/instruction-issuing.

I'm also wondering if the register file and shared memory bandwidth is doubled. G80 is capable of fetching 16 elements per clock (from each, though I'm not sure if it can fetch from both simultaneously at that rate), so I'm wondering if GT200 fetches 32. I've long suspected there's a register bandwidth bottleneck in G80, so it'll be interesting to see if this has changed and therefore a factor in improved TMU utilisation and usage of the MUL - both of which I suspect are bound by register bandwidth in G80.

Jawed

 

I'm sure there'll be a lot of CUDA-using people jumping for joy over the register file increase

Jawed

 

Of course the missing MUL was a serious hit to NVidia's claims for the efficiency of their ALUs. If it routinely achieves 2/3 of the "headline" GFLOPs rating - then it's better to just pretend it doesn't exist, which is why we have G80 as 346GFLOPs, not 518GFLOPs, etc.

Presumably as far as GT200 marketing is concerned, it has more than twice the GFLOPs of G92.

Jawed

 

OK. One thing I'm still unclear about is whether NVidia's architecture has dedicated point-samplers in addition to the "TMU"s or whether in fact the modular configuration of texture fetching/filtering (e.g. addressing unit, fetching, filtering) allows them to run all fetches through the same samplers. It seems likely to be the latter.

Additionally modularisation implies an overhead, as each unit theoretically needs to independently handle its own instruction/operand fetching and resultant posting.

Jawed

 

B3D article:

 

From the slide posted by trini

"Do not distribute"

I kind of feel sorry for those who bought a 9800GX2. I mean, there would be no point in nVIDIA to spend alot of resources especially on the driver side of things to maintain scaling for the GX2 in newer titles to come since its pretty much reached EOL (due to GT200). Quad SLi becomes meaningless once again just like the 7950GX2.

 

I dare to propose, that the batch-size is untouched from the G80, e.g. an additional SIMD array of eight SPs per cluster just increases the threading parallelism...
So now GT200 has a kind of triple-instruction issue, to name it.

I wonder, how this would impact the interpolation rate, compared to G80/92.

 

If I understand correctly the purpose of a cluster is just to share the texturing unit. All of the multiprocessors are independent and contain their own scheduling and operand issue hardware, register file and shared memory. So the number of multiprocessors per cluster won't affect any ALU processing rate but it should increase TMU utilization.

CUDA blocks are distributed at the multiprocessor level and all inter-thread communication is limited to a single multiprocessor.