NVIDIA GF100 & Friends speculation

Now. kow much more power comsumption would the extra memory cause?

Probably not much; since the only other difference is ram amount and the 2070 is slated for somewhere Q3 this year is it likelier to be a ram supply or a chip supply constrain? Pick your poison.
 
No, even the C2050 part comes with 520 GFlops - 630 GFlops. The C2070 has only more memory.
That's not how I interpreted that on the nvidia page. It's true it says a range of 520-630 GFlops for both cards. But my interpretation is that the clocks aren't quite finalized and both cards will fit into that range. However I'd expect C2050 to be closer to the lower end and C2070 closer to the higher end of that range. But I could be wrong, that range there certainly leaves room for speculation :).
 
Probably not much; since the only other difference is ram amount and the 2070 is slated for somewhere Q3 this year is it likelier to be a ram supply or a chip supply constrain? Pick your poison.

Depends on which Tesla is more popular in the market.
 
Now. kow much more power comsumption would the extra memory cause?

Almost none. A 4GB DDR3 10600 DIMM uses like 3 watts. GDDR5 is supposely even lower power consumpiton, although they are clocked to higher performance levels, relatively speaking. 12 more GDDR5 chips probably use 2-3 watts.
 
Almost none. A 4GB DDR3 10600 DIMM uses like 3 watts. GDDR5 is supposely even lower power consumpiton, although they are clocked to higher performance levels, relatively speaking. 12 more GDDR5 chips probably use 2-3 watts.

Why are there heat sinks on the RAM chips? (Or more accurately, why does the board heat spreader cover the RAM chips as well as the GPU?)
 
Almost none. A 4GB DDR3 10600 DIMM uses like 3 watts. GDDR5 is supposely even lower power consumpiton, although they are clocked to higher performance levels, relatively speaking. 12 more GDDR5 chips probably use 2-3 watts.

Why oh why do people GUESS and make up BS numbers when the data is readily available. Its like people want themselves and other people to be clueless idiots.

GDDR5 per device power is in the range of ~3W. So relatively speaking 12 more GDDR5 chips is around ~36W.

Datasheets people, its not like they are a secret conspiracy!
 
Why oh why do people GUESS and make up BS numbers when the data is readily available. Its like people want themselves and other people to be clueless idiots.

GDDR5 per device power is in the range of ~3W. So relatively speaking 12 more GDDR5 chips is around ~36W.

Datasheets people, its not like they are a secret conspiracy!

Good thing you posted that data so we can believe you... oh wait. :rolleyes:

http://www.hynix.com/datasheet/eng/graphics/details/graphics_26_H5GQ1H24AFR.jsp?menu1=01&menu2=04&menu3=05&menuNo=1&m=3&s=5&RK=26

Unless I'm reading it wrong, 1.5v @ 630 mA = 0.945W for a 1Gbit 5Gbps chip, like those in a 5870. Chips in a Tesla board are lower clock, so maybe 0.8W.
 
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Good thing you posted that data so we can believe you... oh wait. :rolleyes:

http://www.hynix.com/datasheet/eng/graphics/details/graphics_26_H5GQ1H24AFR.jsp?menu1=01&menu2=04&menu3=05&menuNo=1&m=3&s=5&RK=26

Unless I'm reading it wrong, 1.5v @ 630 mA = 0.945W for a 1Gbit 5Gbps chip, like those in a 5870. Chips in a Tesla board are lower clock, so maybe 0.8W.

The number I found in the datasheet for burst reads/writes is quite a bit higher, depending on clock around 1.5A (more for the 6gb parts but I'm not assuming tesla gets those). That's over 2W per chip. Too bad the datasheet doesn't mention the actual TDP.
But I think that actually the c2050 will use 24 such chips in clamshell mode (so only 16bit per chip), that drops the amperage to about 1A per chip.
And I don't think c2070 will use twice (hence 48) the chips, I don't know if you can really put them in parallel like ordinary ddr3 ram. But even if it did, it wouldn't increase TDP that much as not all chips can be active at the same time (but don't ask me which of the amperage numbers would apply in this mode...). Rather, I'd suspect 24 2gbit chips, though I'm not sure if the timeframe is right. Hynix said H2 for 2gbit gddr5 parts mass production, but I don't know when they'll actually deliver - but it would definitely explain why it appears later (and using 2gbit chips instead of 1gbit shouldn't increase TDP).
 
That would really suck if they did that.

Nvidia, the way it's meant be renamed...

It's getting extremely tiresome no? Honestly it would surprise me a whole lot if Fermi was competitive in its first incarnation, maybe by D0/1 they Nv can get competitive silicon out. By then it will be extremely late in the day.
 
Good thing you posted that data so we can believe you... oh wait. :rolleyes:

http://www.hynix.com/datasheet/eng/graphics/details/graphics_26_H5GQ1H24AFR.jsp?menu1=01&menu2=04&menu3=05&menuNo=1&m=3&s=5&RK=26

Unless I'm reading it wrong, 1.5v @ 630 mA = 0.945W for a 1Gbit 5Gbps chip, like those in a 5870. Chips in a Tesla board are lower clock, so maybe 0.8W.

way to not know how to read a data sheet. One might like to actually use a IDD value that has some relation to actually doing something like IDD4 or IDD7. Since we are looking for an effective TDP in use, IDD4R was chosen as it has the highest current. These number should actually be the low side of actual TDP because they are primarily active current, add in static currents, associated ref voltages and currents, etc, and the TDP values are higher, so my ~3W is a good rough estimate.
 
Yeah that makes sense. 4xx series for DX11. GTX 470 though? Does that indicate it's not going to be much slower than the big dog?

It could indicate one of three things:

1) GTx 4xx are all DX11 (GTx 3xx are all DX10.1)

2) GTX 470 is meant to compete against HD 5870 (can't name it GTX 460, right?)

3) GTX 470 will be closer in performance to GTX 480 high than it will be to the GTX 4xx (450?) midrange cards
 
The number I found in the datasheet for burst reads/writes is quite a bit higher, depending on clock around 1.5A (more for the 6gb parts but I'm not assuming tesla gets those). That's over 2W per chip. Too bad the datasheet doesn't mention the actual TDP.
But I think that actually the c2050 will use 24 such chips in clamshell mode (so only 16bit per chip), that drops the amperage to about 1A per chip.
And I don't think c2070 will use twice (hence 48) the chips, I don't know if you can really put them in parallel like ordinary ddr3 ram. But even if it did, it wouldn't increase TDP that much as not all chips can be active at the same time (but don't ask me which of the amperage numbers would apply in this mode...). Rather, I'd suspect 24 2gbit chips, though I'm not sure if the timeframe is right. Hynix said H2 for 2gbit gddr5 parts mass production, but I don't know when they'll actually deliver - but it would definitely explain why it appears later (and using 2gbit chips instead of 1gbit shouldn't increase TDP).

AFAIK, 2070 will use DDR3.
 
way to not know how to read a data sheet. One might like to actually use a IDD value that has some relation to actually doing something like IDD4 or IDD7. Since we are looking for an effective TDP in use, IDD4R was chosen as it has the highest current. These number should actually be the low side of actual TDP because they are primarily active current, add in static currents, associated ref voltages and currents, etc, and the TDP values are higher, so my ~3W is a good rough estimate.

So uhh, you get mad at me for not knowing and giving and estimate based on what I've read, but you don't know yourself and are giving an "estimate"(read: guess), do I read that correctly? :LOL:

This is wehre I got my estimate from, btw: http://www.dailytech.com/article.aspx?newsid=17570

~3W per 4GB DIMM, though I suppose those are low power products...
 
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