The number I found in the datasheet for burst reads/writes is quite a bit higher, depending on clock around 1.5A (more for the 6gb parts but I'm not assuming tesla gets those). That's over 2W per chip. Too bad the datasheet doesn't mention the actual TDP.
But I think that actually the c2050 will use 24 such chips in clamshell mode (so only 16bit per chip), that drops the amperage to about 1A per chip.
And I don't think c2070 will use twice (hence 48) the chips, I don't know if you can really put them in parallel like ordinary ddr3 ram. But even if it did, it wouldn't increase TDP that much as not all chips can be active at the same time (but don't ask me which of the amperage numbers would apply in this mode...). Rather, I'd suspect 24 2gbit chips, though I'm not sure if the timeframe is right. Hynix said H2 for 2gbit gddr5 parts mass production, but I don't know when they'll actually deliver - but it would definitely explain why it appears later (and using 2gbit chips instead of 1gbit shouldn't increase TDP).