Nvidia Blackwell Architecture Speculation

[TopSpoiler]

Is there a reason IHVs have mostly avoided odd numbers of memory channels? Are they better in pairs or something?

I found this answer:

Memory transaction size

That’s a lot of questions External Media I’ll just try to answer two… On G80 to GT200 architectures, 32-bit GDDR3 RAM chips are grouped in pairs, and every transaction is routed to a pair of chips put in parallel. This is why bus widths of NVidia GPUs are all 64-bit multiples. Then, each...

forums.developer.nvidia.com

 

[arandomguy]

I found this answer:

Memory transaction size

That’s a lot of questions External Media I’ll just try to answer two… On G80 to GT200 architectures, 32-bit GDDR3 RAM chips are grouped in pairs, and every transaction is routed to a pair of chips put in parallel. This is why bus widths of NVidia GPUs are all 64-bit multiples. Then, each...

forums.developer.nvidia.com

I believe this was changed with Pascal.

GM204 -

https://tpucdn.com/gpu-specs/images/g/767-block-diagram.jpg

GP104 -

https://tpucdn.com/gpu-specs/images/g/793-block-diagram.jpg

Hence likely also why the we saw 11 channel configurations used for Pascal (1080ti) and the next generation in Turing (2080ti) as well.