TopSpoiler
Regular
I found this answer:Is there a reason IHVs have mostly avoided odd numbers of memory channels? Are they better in pairs or something?

Memory transaction size
That’s a lot of questions External Media I’ll just try to answer two… On G80 to GT200 architectures, 32-bit GDDR3 RAM chips are grouped in pairs, and every transaction is routed to a pair of chips put in parallel. This is why bus widths of NVidia GPUs are all 64-bit multiples. Then, each...
