NVIDIA GF100 & Friends speculation

Well, even if they're uncorrelated, purely by chance a significant fraction of them will be clustered.

You've got no idea if they will be clustered in the middle of a chip, or at a point where the corners of four chips meet, thus taking out all four chips. It might also be the case that a cluster can destroy a chip or two, where those same defects spread over a larger area will allow parts of a chip to be fused off to still become a viable product.

Over a large enough sample of wafers, it probably all evens out anyway, and the defect rate averages out to approximately the same number of defects per wafer regardless of whether an individual wafer has it's defects all spread out or in clusters. This of course assumes that defects are random, and not influenced by other factors.
 
You've got no idea if they will be clustered in the middle of a chip, or at a point where the corners of four chips meet, thus taking out all four chips. It might also be the case that a cluster can destroy a chip or two, where those same defects spread over a larger area will allow parts of a chip to be fused off to still become a viable product.
Well, the only clustering that matters is clustering within one chip.

But just as a small illustration on randomness:
pointb.jpg

pointa.jpg


From this blog post:
http://telescoper.wordpress.com/2009/04/04/points-and-poisson-davril/

One of the two images has points that are completely uncorrelated with one another. The other image has points that have very important correlations (meaning that the position of the next point depends critically upon the positions of existing points). Which, do you think, is which?
 
Well, the only clustering that matters is clustering within one chip.

Then you have to take into account the fact that a larger chip will have more clustering within it compared to any given smaller chip on the same wafer.

One of the two images has points that are completely uncorrelated with one another. The other image has points that have very important correlations (meaning that the position of the next point depends critically upon the positions of existing points). Which, do you think, is which?

I'd guess the bottom one is random, and the top one is where every point is correlated to the other. The top one is too evenly spread out to be random.
 
Wouldn't defects tend to be more clustered as they are not all random? So one die may end up with more than its fair share of defects. In addition to this are the percentages the rough number of 'perfect' dies which can be fully enabled?
The whole thing is just a very rough model. See the article I linked earlier which talks about how to model yields. Pick your poison. I'm certainly not claiming it's accurate! I merely nosed around a little and produced an illustration showing how yields can be quite dreadful.

People should read the articles I linked.

Jawed
 
I guess the top one is correlated and the bottom one is random. The top one looks pretty smooth whereas random numbers don't mean equal distribution.
 
The whole thing is just a very rough model. See the article I linked earlier which talks about how to model yields. Pick your poison. I'm certainly not claiming it's accurate! I merely nosed around a little and produced an illustration showing how yields can be quite dreadful.

People should read the articles I linked.

Jawed

I read it but it was a little beyond my comprehension level. :(
 
Fudzilla

After couple of inquiries we found out that even though you can get estimated performance figures based on what partners are looking at right now, these are still not final as Nvidia is yet to give out a word about the final clocks of the GTX 470. The safest guess is that it will be around 20 to 25 percent faster than the Geforce GTX 285, which puts it somewhere between the HD 5850 and the HD 5870.

Why is even NV's PR agency guessing so low?
 
top correlated, bottom random
Indeed, you all got it right :)

This visual example, I think, is a particularly good illustration of the human capacity to see patterns where there are none. The majority of people think of the bottom image as being the correlated one, not the top image. I'd be willing to bet that even among those who got it correct in this thread, most of you probably, at first glance, felt that the top one was right (and therefore were more inclined to pick the bottom because you knew I was trying to be tricky), though I'm sure some may be familiar enough with this sort of thing that they had no problem picking the right answer.

The first example is basically a set of randomly-distributed points where the next point is never allowed to get too close to any existing one. The second one is just randomly-distributed points (with a uniform distribution, of course).

So if you have 15 defects on a wafer, even if they are completely unrelated to one another, then you're highly unlikely to have 15 dead chips (unless your chips are really, really small). More likely is that some of them, just by chance, land on the same chip. You can think of the defects as ending up dotted around the wafer as in that second image.

Now, it's possible that the cause of the defects makes it so that they tend to cluster even more than this, but my suspicion is that it isn't possible for them to cluster less.
 
Now, it's possible that the cause of the defects makes it so that they tend to cluster even more than this, but my suspicion is that it isn't possible for them to cluster less.

That may not help much though. When looked at across many wafers, there's no doubt that on average, larger chips are more affected by defects than smaller chips. It's not likely that all the defects will cluster in one chip, leaving all the others on that wafer to be perfect. Even if you could say that a cluster of defects in one place will create one dead chip and one good chip instead of two salvage parts, I'm not sure that's any better for Nvidia in the long run.

Jawed's finger-in-the-air numbers are still a good illustration of how yields between a large chip and a small chip can be dramatically different given the same defects on a run of wafers. Nvidia has to have a lot less defects to make the same number of chips than ATI does, and I'm sure this is one of the major problems they've been having with getting GF100 out the door.
 
It's a fair bit smaller than that, by about 100mm², methinks.
Defect density of 0.1, 480mm² would result in 32.9%.

By the way, my earlier figures are tainted by a brain fart: an inch is 25.4mm, not 25.6mm, sigh. Cypress at 0.1 should be 45.7%, not 46.3%. Just in case anyone runs the numbers and wonders what the hell I did.

Jawed
 
GF100 doesn't need to make money in high end consumer market. The R&D has been done for mid range and low end parts. The design is *very* modular. NV has the immensely profitable professional market at it's feet and GF100 has a lot of potential to win large parts of HPC market.

How much impact Eyefinity has in pro markets remains to be seen, but it has been said that it has immense potential to do well there.
 
GF100 doesn't need to make money in high end consumer market. The R&D has been done for mid range and low end parts. The design is *very* modular. NV has the immensely profitable professional market at it's feet and GF100 has a lot of potential to win large parts of HPC market.

Gotta get that product out the door first. It's no good being modular and handwaving about not needing to make money, if you can't make the product in the first place.

Do you think Nvidia will send me a high-end GF100 for free, as they don't need to make any money on it? :LOL:
 
I read it but it was a little beyond my comprehension level. :(
In the graph you can see there isn't a massive difference between the models. The Bose-Einstein model is for N=10, so for N=15.5 as I used, it would be lower than the others.

The others don't model number of mask layers - so they count defect density as the "average" of all layers, I presume, which is much higher than for a single layer. Also there's no accounting for wafer size (Seeds looks like a model for small wafers).

Nothing models the sensitivity of each layer to defects. Some layers are super-sensitive and other layers relatively tolerant it seems. Depends on the size of features on those layers and electrical characteristics.

There's a model for clustering:

The negative binomial model uses a cluster factor, a, to estimate the tendency of killer defects to depart from total randomness. A smaller value of a means a higher degree of clustering and greater variation in Do across the wafer. Alternatively, as a approaches infinity one gets the modified Poisson yield model.
So, when talking about Do as reported by TSMC, one needs to account for the fact that TSMC is using the Bose-Einstein model, and this defect density is per layer, whereas the other models require defect density to be averaged across all layers. So TSMC's defect density number appears much lower.

So my first post on this topic, which said, "Average defect counts were 34-45 per wafer, and are now down to 11-34 per wafer" is wrong as that doesn't take account of layers.

Jawed
 
Gotta get that product out the door first. It's no good being modular and handwaving about not needing to make money, if you can't make the product in the first place.
Fair enough.
Do you think Nvidia will send me a high-end GF100 for free, as they don't need to make any money on it? :LOL:

Not needing to make money from one part in one segment of market is different from not wanting to make money off it. ;)

FWIW, I don't think they'll send me a high-end GF100 for free. :-|
 
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