DaveBaumann said:
Its not dumb Vince, your statement that the PC vendors have an "(in)ability to create usable and farsignted standard between each component" is clearly incorrect as you have proved yourself by the very fact that it can be applied beyond the scope of the PC environment and used to a full context.
No, you just don't understand what's being stated. Very simple, and you're going to do all the thinking:
- I have GPU Gn, CPU Cn, Storage Sn, which of the following would more closely approximate the eq. point of greastest preformance:
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- Closed System A: [GPU G1, CPU C1, Storage S1] with custom interconnections and system optimization; or:
- Open System B: Random combination of [GPU Gn, CPU Cn, Storage Sn] |n=1...1E5
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The PC will allways lose out to a closed-set enviroment, especially in the PC paradigm we have in which there is little thinking of the system on a holistic level. Each vender is concerned primarily with their given component and there is little cooperative work. Hell, look at the history of PCI, AGP and - finally - PCI-Express. AGP texturing anyone?
DaveBaumann said:
The curious element about your last point is that the Cell paradigm is that it is designed to be used in a multitude of devices so the hardware contructs it employs are going to have to be less specific by design, in some areas, than the pure device its going to be utilised in.
I question the convention wisdom that applied, and both of us talked about, back in the 1999 period when DX7 was around with DX8 on the horizon and all the buzz was about the move to more programmability and the questions of fixed-functionality verse programmability and what preformance delta there would be. I feel that we were correct for out time, but the paradigm (I need a new word... situation) has changed with the influx of logic that's been happening and will only accelerate in the next two years tremedously.
When we were talking about a 20M-odd transistor NV15, the balance is alot finer than it is when we're talking about
a Broadband Engine or R500 that could be approaching a Billion transistors. We've, IMHO, reached a point where the bounds are on sheer computation and bandwith in dynamic applications. It's possible to design around a modular architecture that's focused on these types of applications which can be scaled down to the low-end apps which have a low resource budget, while retaining cost effeciency due to process advances.
For example, as the ATI guys have told me and you've mentioned on the site from time to time, general computation is moving to the GPU. Not to mention names, but somone here and I were discussing sequencing on them. A GPU is, I'm betting you're going to say, highly tuned to graphic applications but it can still run anything. With the move to a unified shader (I don't know but would guess the ALU they'd use is more akin to a current VS [over current PS constructs, which is why I stated
this] which is akin to an APU) this just becomes more and more feasible.