According to Google Translate (including the translated name
)https://finance.technews.tw/2019/12/20/nvidia-7nm-for-tsmc/
Nvidia Ampere Discussion [2020-05-14]
- Thread starter Man from Atlantis
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Man from Atlantis
Veteran
According to Google Translate (including the translated name
https://finance.technews.tw/2019/12/20/nvidia-7nm-for-tsmc/
What I understand from the quote regarding 7nm TSMC will get the most orders, but according to rumors Nvidia will use 8nm LPP Samsung for gaming Ampere. So it's apples and oranges.
If Samsung want to make a splash for their (upcoming piles of) HBM2E, an RTX 3090 with stacks of HBM2E would do it. Since Samsung is in deep enough to be doing the 40GB HBM2E for A100, maybe someone showed Jensen what he could do with Ampere + HBM for gamers? Thinking about how AMD engineers whipped up an unexpected "thread-ripper", what if someone suggested a "3090" as "A100 for gamers"?
iMacmatician
Regular
I haven't been following NVIDIA stuff closely, but could NVIDIA pull an Apple A9 and dual-source gaming GPUs (for example a "GA106") between TSMC 7 nm and Samsung 8 nm LPP?
It would need to be separately designed for each process. Most likely it's the same split as before, one or two lowend chips to Samsung, rest to TSMC
That makes no sense though. Why would Nvidia go through the effort of designing A100 for two different fabs and give one a much smaller order? In the past Nvidia let Samsung fab their cheap low power consumer GPUs while TSMC handled the high end. Before all this Ampere talk, Orin was rumoured to be on Samsungs 8LPP node. I think the ”insiders” are mixing up rumours
Maybe consumer Ampere is Samsung 8LPP i dunno but highly unlikely Samsung is fabbing small order of A100 for Nvidia. Those 7nm orders must be for a different product in that case
Bondrewd
Veteran
No because those have wildly different design rules.
Frenetic Pony
Veteran
The 7nm stuff pretty much needs to be from TSMC, they're the only ones who could make a reticle limit 7nm dies reliably enough to get just about any good ones out, and they're already charging a ton. Speaking of, as the chip is at the TSMC 7nm reticle limit, and in general they're pushing 50% higher density than Samsung 8nm, I don't think that monster would even fit on 8nm.
TSMC 7nm (HPC) is basically already probed with Ampere GA100 claiming ~65MT/mm^2 and AMD Renoir being calculated to be somewhere just below that.
Samsung 8nm is claiming ~61MT/mm^2, which is hardly half of the density. Either way, Samsung will either learn how to make larger dies or what's left of IBM Power10 will fail. Given IBM's recent lack of fortune in netting HPC contracts, it is possible. Samsung density claims for 10nm seem to have checked out (with Snapdragon 845 being estimated around 56.4MT/mm^2 by Anandtech), so I don't see any reason to doubt their current claims for 8nm.
While TSMC's current 7nm mobile variant, their more advanced 7nm EUV, and 5nm processes all claim higher densities, it doesn't seem to be relevant for this upcoming generation of graphics cards.
Frenetic Pony
Veteran
That's actual density of a shipping chip for TSMC versus claimed density of Samsung. I went apples to apples, TSMC claimed maximum density to Samsung claimed maximum. Unless Nvidia managed to hit Samsung's absolutely ideal PR numbers but not TSMC's, it's just not a chip that's going to fit on 8nm.
IMO, Nvidia has pretty much reached TSMC's claimed 7nm HPC density and AMD is close as well.
I'll note, Samsung's "PR numbers" for 10nm density were slightly lower/worse vs later shipping silicon - Qualcomm exceeded Samsung's 10nm density claims by ~10% (of course, the usual debate of "what is transistor density and how to measure transistor density" rages on). Again, I see no reason to disbelieve Samsung's claims for their 8nm processes, a derivative of their 10nm process.
Even if Nvidia only managed to match Qualcomm's Snapdragon 845 (a 10nm product)'s transistor density, that would still be 56.4MT/mm^2, far better than the "50%" claim. Again, this is against both shipping products in the real world and TSMC's own claims for their 7nm HPC process (claimed at 66.7 MT/mm^2, FWIW).
Frenetic Pony
Veteran
According to this TSMC is claiming 90MT/mm^2 for 7nm https://semiwiki.com/semiconductor-...foundry/8157-tsmc-and-samsung-5nm-comparison/
That's High Density Cells, High Performance Cells are less dense and offer around 65 MT/mm^2 https://en.wikichip.org/wiki/7_nm_lithography_process#TSMC
Are Qualcomm’s mobile SoCs a relevant data point for an Nvidia chip? Kirin 980 achieved over 90MT/mm^2 at TSMC. That seems a more appropriate comparison.
There’s no reason to assume nvidia will match Qualcomm’s results.
Bondrewd
Veteran
Real world density is a very tricky thing impacted by multitude of design considerations.
Apparently then, the design choices made for XBX were similar (or at least had similar consequences in terms of x-tors/mm²) to those of other RDNA-products. Navi's transistor density is in the same league.
Bondrewd
Veteran
Yuh.
Most RDNA and RDNA2 parts should have comparable density.
The relative high transistor density of the A100, might possibly be a result from switching to the latest N7+ process.
This one is said to be 1.2x more dense as vanilla 7nm. As it involves EUV it could be too expensive for mass production.
Edit: I'm probably wrong about this as N7+ seems to be high density and not high performance.
This one is said to be 1.2x more dense as vanilla 7nm. As it involves EUV it could be too expensive for mass production.
Edit: I'm probably wrong about this as N7+ seems to be high density and not high performance.
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