Nvidia Ampere Discussion [2020-05-14]

https://blogs.nvidia.com/blog/2021/...582&linkId=100000040843726#cid=_so-twit_en-us

 

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Speaking of RT. Nvidias "Best Practices" mention "Use triangle geometries when possible. Hardware excels in performing ray-triangle intersections. Ray-box intersections are accelerated too, but you get the most out of the hardware when tracing against triangle geometries."

I was under the impression, that Nvidia as well as AMD could perform 4 Box intersections or 1 Triangle intersection per Unit. Has anyone seen more documentation on Ampere (and possibly Turing) in this matter?

 

Nvidia has never shared the number of box or triangle intersections per clock in shipping products. If I recall correctly their patents referred to compressing 8 boxes into a single cache line so that may be a hint.

"In one embodiment, the TTU may include four traversal units to test up to eight child nodes for intersection with the ray in parallel."

https://patents.google.com/patent/US9582607B2/en

 

Ampere's triangle intersection rate is twice that of Turing's isn't it?

The page was written before Ampere came along, August 2020.

Is Ray-box used primarily (solely?) for procedural geometry?

 

All geometry (triangles and procedural) is encapsulated in boxes. It's not a choice between boxes vs triangles.

 

I guess that's just a poor wording. What's meant here is that you should not use custom primitives instead of triangles because custom primitives would not be HW accelerated in that case.

 

Poor wording when you have to make sure that developers do understand exactly what the DOs and DON'Ts for Raytracing are?