NVidia Ada Speculation, Rumours and Discussion

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Kaotik said:
Like I said, they still talk about it, but even process names don't refer to nanometers anymore (it's N5 instead of 5nm etc, Intel 7 instead of 10nm and so on)
The little relation "nanometers" still had with reality was lost for good when we moved to finfets. The nm is supposed to refer to smallest feature size, gate length in transistor. There isn't too detailed information on all processes, but 14nm has enough details for 3 manufacturers. Depending on manufacturer "14nm gate length" is actually 18 to 30 nm
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That’s been the case for a long time now. But there’s no point in avoiding nm nomenclature until manufacturers stop using it first.
 
Kaotik said:
People really should stop talking about nm when talking about processes, they have nothing to do with anything anymore (and while manufacturers still use them, the actual process names don't)
For example, TSMC doesn't have 4 nm process, they have N5, N5P, N4, 4N (nvidia wants own name for their specific config for whatever reason) etc which belong to their "5nm class processes" but not one of them has anything 5nm "sized"
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Nobody here is confused about any of this. Nor are anybody who it actually matters to. The only 'problem' surrounding this topic basically comes from occasional clueless tech press reporters.

So long as we're all on the same page and know what's being talked about, there's literally no harm at all in stating things whichever way. Specificity just for specificity's sake is completely worthless.
 
Kaotik said:
For example, TSMC doesn't have 4 nm process, they have N5, N5P, N4, 4N (nvidia wants own name for their specific config for whatever reason) etc which belong to their "5nm class processes"
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1. The reason why Nv "wants" their own name is because the process is actually customized for their production needs. It's actually a separate version of TSMC's N5 process - in much the same vein as N5P and N4 are. This has been shown to be the case with some previous Nv customized nodes I believe, don't remember which ones. (I think it was with A100's version of N7? Which didn't actually have its own name which is a bit funny.)

2. "5nm class processes" isn't at all correct either since none of these processes are "5nm" technically speaking. Which is also why it's "N5" and not "5nm". A more correct term would be "N5 family of processes" as this one was the main basis for them all.
 
DegustatoR said:
1. The reason why Nv "wants" their own name is because the process is actually customized for their production needs. It's actually a separate version of TSMC's N5 process - in much the same vein as N5P and N4 are. This has been shown to be the case with some previous Nv customized nodes I believe, don't remember which ones. (I think it was with A100's version of N7? Which didn't actually have its own name which is a bit funny.)

2. "5nm class processes" isn't at all correct either since none of these processes are "5nm" technically speaking. Which is also why it's "N5" and not "5nm". A more correct term would be "N5 family of processes" as this one was the main basis for them all.
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1. Today every customer gets to customize the process parameters within certain limits for their product, nothing shown anywhere suggests NVIDIAs "custom processes" are anything more. (edit: for example AMD talks about "customized processes" too, but don't put names on them)
2. Yeah, I raised that point myself too, that specific post didn't carry the point through properly
 
So according to the rumour mill we've got a 4080 that hits 15k TSE at 320 watts, and a 4060 that hits 6k TSE at 240 watts. Or nearly a 2x difference in performance per watt across the stack?

People really need to not trust random twitter accounts posting crap
 
Ideas for new uses by NVidia for tensor cores:
  1. Frame doubler, using AI-driven interpolation. Many games use a G-buffer and often there are motion vectors associated with G-buffers. In general, I presume, G-buffers are fully complete less than half-way through the time it takes to render a frame. This would enable an inference engine to take two frames' G-buffers, motion vectors (if available) and render targets to interpolate a third frame (underlined in the list below) while the fourth frame is being fully rendered (turning 60fps rendering into 120fps display):
    • 8.333ms: frame 1 inferenced G-buffer, motion-vectors and render target
    • 16.67ms: frame 2 real G-buffer, motion-vectors and render target
    • 25.00ms: frame 3 inferenced G-buffer, motion-vectors and render target generated while frame 4 is being shaded
    • 33.33ms: frame 4 real G-buffer, motion-vectors and render target
  2. Ray-generation optimiser. Generating the best rays to trace seems to be a black art. It's unclear to me how developers tune their algorithms to do this. I'm going to guess that with some AI inferencing that takes the denoiser input and some ray generation statistics, the next frame's ray generation can be steered for higher ray count per pixel where quality matters most. This would enable faster stabilisation for algorithms such as ambient occlusion or reflections where disocclusion and rapid panning cause highly visible artefacts due to low ray count per pixel.
I'm going to guess that these ideas would use a lot of memory. I get the sense that the next generation is going to be more generous with memory, so that shouldn't be a problem.

I'm expecting these kinds of ideas to make use of the DLL-driven plug-in architecture we've seen with DLSS, activated by developers as a new option in the graphics settings menus.

How much of this kind of stuff can be back-ported to Turing or Ampere? What would make these features uniquely available on Ada?
 
I wouldn't mind it if there were 2 versions of the higher end cards... label them with a suffix something like 2K & 4K. Same chips/core counts, but less memory & bandwidth for the 2K version... at a nice discount. I (and I imagine many others... 2/3rds steam though decreasing) game at 1080p, but I still want high framerates, high min framerate, all the eye candy, etc...
 
It depends on what the primary bottleneck is and where. If bandwidth is limiting me to a max framerate above my monitors refresh IDGAF; if it is affecting mins, it matters. But you clearly just want to argue, so you can do that with yourself...

Anyway, a video card producing company looking to increase market share might be rewarded for throwing some consideration towards the biggest slice of the pie.
 
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