No CELL revealed at IBM event. Sony Licenses POWER..
- Thread starter Deadmeat
- Start date
...
Thank you for admitting.
I already did several calculations against SCEI and IBM's logic gate density and it shows that 65 nm CELL is a single PE device.(SCEI might fit two if they really went insane and not care about cost, but I strongly dbout it). The most you can get out of a single PE device @ 2 Ghz(SCEI can't go for high clock beceause that kills the yield) is at most 128 GFLOPS. I just don't make predictions out of thin air, I actually do some calculations before making such claims...
David_South#1
Banned
Few words,
Sony IBM and Toshiba have all directly stated the need for reconfigurable chips.
The concern is that as chip density and complexity increase, successful chip production (Yield rates) will fall. Also over time with the ever narrower width of processor wiring, fault tolerance will become a great concern.
So basically all major chip makers share this concern. The present solution is something called Field Programmable Gate Array (FPGA). This isn’t new technology. It’s just costly in that it takes more gates=processing area=expense to include=unnecessary for most applications.
At one point it became my belief that cell processors would most definitely have a FPGA features. How else do you convert processing circuits to memory circuits, and vis vis? (Something that cell was said to be able to do.)
Second all of these comments over the term “Power†lack the simple sight that any and all proprietary circuit design or intellectual property involving processors and IBM falls under the term Power architecure.
PowerPC
Power###
Power this, Power that, "I have the power." ;D
And if Sony has license Silicon on insulator, low K doping, etc then Sony has been licensing Power chip design since nearly the beginning of this Cell ambiguity.
Anyhow I hope this makes some sense to you and opens up things for people.
Sony IBM and Toshiba have all directly stated the need for reconfigurable chips.
The concern is that as chip density and complexity increase, successful chip production (Yield rates) will fall. Also over time with the ever narrower width of processor wiring, fault tolerance will become a great concern.
So basically all major chip makers share this concern. The present solution is something called Field Programmable Gate Array (FPGA). This isn’t new technology. It’s just costly in that it takes more gates=processing area=expense to include=unnecessary for most applications.
At one point it became my belief that cell processors would most definitely have a FPGA features. How else do you convert processing circuits to memory circuits, and vis vis? (Something that cell was said to be able to do.)
Second all of these comments over the term “Power†lack the simple sight that any and all proprietary circuit design or intellectual property involving processors and IBM falls under the term Power architecure.
PowerPC
Power###
Power this, Power that, "I have the power." ;D
And if Sony has license Silicon on insulator, low K doping, etc then Sony has been licensing Power chip design since nearly the beginning of this Cell ambiguity.
Anyhow I hope this makes some sense to you and opens up things for people.
Teasy, Zidane,
I thought it was common knowledge that i am both Deadmeat AND chap (all the different versions), and of course L-B...
I don't think i'm posting enough as LB, so i thought i'd create other usernames... Ok this is getting freaky.
(ok i thought i'd let off some steam around the thread, things got a little bit tense...)
I thought it was common knowledge that i am both Deadmeat AND chap (all the different versions), and of course L-B...
I don't think i'm posting enough as LB, so i thought i'd create other usernames... Ok this is getting freaky.(ok i thought i'd let off some steam around the thread, things got a little bit tense...)
David_South#1
Banned
Nobie,
You are not alone in that right. Many others have said the same thing.
But it has bugged me a for a long time that people imagine the PU of a Processor Element to be an IBM Power# chip. Why do people have this assumption and where did it spread??
The main reason it bugs me is that the idea (to me at least) projects the notion that a PU is packaged separate from the APU. The PU is like the air traffic controller of The Element. Remove the controller from tarmac and you delay it's ability to update and govern take off and landings. Basically a separate chip means increased latency and of course much greater production costs. And integrated PU core is likely the best guess.
Something else I want to comment on. I hate when I see it, but many people include the PU as a workload processor in an element. The PU doesn't perform the work per say, it just governs and balances, checking and directing the APU. So please no more a PE has 9 processor. Instead 8+1, 4+1, 2+1 etc is fine but please doesn't combine the numbers.
To understand this, view these numbers like a gun. The PU could perform calculations like an APU if it were needed to, just like the chamber of a gun could hold a bullet in addition to the magazine. However a chamber is meant to fire bullets and not hold them. So please don't shoot yourself by making this mistake.
---
I certainly can't tell you that Power4 is not going to become the PU of an element and prove it as a fact. But Power4 is a dual core processor and the PU as I understanding it has need for only one core. So a Power4 will processor will not be the PU of a PE.
Now I'm not going to say that a variant on Power4 couldn't become the PU. Suck things have happened before (A Single core PowerPC 970). But a Power4 or separately packaged chip doesn't seem likely to me.
You are not alone in that right. Many others have said the same thing.
But it has bugged me a for a long time that people imagine the PU of a Processor Element to be an IBM Power# chip. Why do people have this assumption and where did it spread??
The main reason it bugs me is that the idea (to me at least) projects the notion that a PU is packaged separate from the APU. The PU is like the air traffic controller of The Element. Remove the controller from tarmac and you delay it's ability to update and govern take off and landings. Basically a separate chip means increased latency and of course much greater production costs. And integrated PU core is likely the best guess.
Something else I want to comment on. I hate when I see it, but many people include the PU as a workload processor in an element. The PU doesn't perform the work per say, it just governs and balances, checking and directing the APU. So please no more a PE has 9 processor. Instead 8+1, 4+1, 2+1 etc is fine but please doesn't combine the numbers.
To understand this, view these numbers like a gun. The PU could perform calculations like an APU if it were needed to, just like the chamber of a gun could hold a bullet in addition to the magazine. However a chamber is meant to fire bullets and not hold them. So please don't shoot yourself by making this mistake.
---
I certainly can't tell you that Power4 is not going to become the PU of an element and prove it as a fact. But Power4 is a dual core processor and the PU as I understanding it has need for only one core. So a Power4 will processor will not be the PU of a PE.
Now I'm not going to say that a variant on Power4 couldn't become the PU. Suck things have happened before (A Single core PowerPC 970). But a Power4 or separately packaged chip doesn't seem likely to me.
...
I wonder if the CELL unveiling would be like "Power Everywhere(TM)" event of yesterday.
I searched around to see if IBM announced any new ground-breaking product; they announced nothing new. All they did can be summerized in one sentence, "IBM does ARM". Take an old core like PPC440, pack its source code with some VHDL toolkit and make it downloadable over the Internet. IBM marketing men then go wild and say "Hey, our CPU source is downloadable, you build your own ASIC with this and we will fab it for you for a certain fee." The trouble is, ARM has been doing this for a decade, minus the fabbing service. So what's new here? A new marketing buzz and hype of same old technology.
CELL, as it stands now, is going to be some Power4 core with 8 active APUs; 4 times what EE had. Nothing really revolutionary here technology wise, but SCEI marketing men will turn it into the greatest thing since ENIAC the first computer. Read my sig file down below...
I wonder if the CELL unveiling would be like "Power Everywhere(TM)" event of yesterday.
I searched around to see if IBM announced any new ground-breaking product; they announced nothing new. All they did can be summerized in one sentence, "IBM does ARM". Take an old core like PPC440, pack its source code with some VHDL toolkit and make it downloadable over the Internet. IBM marketing men then go wild and say "Hey, our CPU source is downloadable, you build your own ASIC with this and we will fab it for you for a certain fee." The trouble is, ARM has been doing this for a decade, minus the fabbing service. So what's new here? A new marketing buzz and hype of same old technology.
CELL, as it stands now, is going to be some Power4 core with 8 active APUs; 4 times what EE had. Nothing really revolutionary here technology wise, but SCEI marketing men will turn it into the greatest thing since ENIAC the first computer. Read my sig file down below...
Re: ...
First off, I don't think you have to devote your entire life to downplaying the architecture. I'd say if they do have a scalable and pervasive architecture which allows for seemless data mobility, it would be pretty big. Again, lets wait and see before you talk.
Also, ENIAC wasn't the first computer. I'd say the Analytical Engine is closer, but still doesn't end the story. The US Census in 1890 was automated by a calculating machine and there were automata before the 17th century IIRC.
And even if you're refering to Electrical machines, there were Relay based Computers in the 40s and even if your talking about Vacuum-tube based computing, Colossus beat ENIAC by a few years AFAIK. Or maybe SSEM?
And we've all read your sig, we just don't pay attention.
Deadmeat said:
First off, I don't think you have to devote your entire life to downplaying the architecture. I'd say if they do have a scalable and pervasive architecture which allows for seemless data mobility, it would be pretty big. Again, lets wait and see before you talk.
Also, ENIAC wasn't the first computer. I'd say the Analytical Engine is closer, but still doesn't end the story. The US Census in 1890 was automated by a calculating machine and there were automata before the 17th century IIRC.
And even if you're refering to Electrical machines, there were Relay based Computers in the 40s and even if your talking about Vacuum-tube based computing, Colossus beat ENIAC by a few years AFAIK. Or maybe SSEM?
And we've all read your sig, we just don't pay attention.
Because it is most likely to be one. If we put blinders on and only see paralels from PS2 like Deadmeat does, PU actually becomes the main processing element for all general purpose code.
And while I don't really agree with that assessment of his, I do think that as long as PUs are fast enough - the early applications will likely do exactly that - run most if not all of application logic code on them.
It's not that APUs aren't suited to those tasks (everything in patents actually suggests the contrary), it's the fact that most current programming approaches used in games aren't there yet.
That aside, PU needs to be a powerfull processor for this to be a balanced setup. The last thing you want is PS2-like situation where R5900 core is the weakest link in the chain 95% of the time, and ends up dragging the rest of otherwise fast specialized units down with it.
Megadrive1988
Veteran
Some interesting news from aces
http://www.aceshardware.com/
IBM:
PPC 970 = 90W / 25M transistors = 3.60W/M transistor
PPC 970FX = 55W / 28M transistors = 1.96W/M transistors
Percentage improvement = 45.6% less power
Intel:
P4 130nm = 82W / 28M transistors = 2.93W/M transistors
P4 90nm = 103W / 65M transistors = 1.58W/M transistors
Percentage improvement = 46.1% less power
This is good news as they are able to keep droping power needed which will reduce heat out put
So perhaps we will see a 4ghz cell .
Then again even those the p4 uses less than 46.1% power they still had massive problems clocking it to 3.2 ghz because of the heat
http://www.aceshardware.com/
IBM:
PPC 970 = 90W / 25M transistors = 3.60W/M transistor
PPC 970FX = 55W / 28M transistors = 1.96W/M transistors
Percentage improvement = 45.6% less power
Intel:
P4 130nm = 82W / 28M transistors = 2.93W/M transistors
P4 90nm = 103W / 65M transistors = 1.58W/M transistors
Percentage improvement = 46.1% less power
This is good news as they are able to keep droping power needed which will reduce heat out put
So perhaps we will see a 4ghz cell .
Then again even those the p4 uses less than 46.1% power they still had massive problems clocking it to 3.2 ghz because of the heat
