No CELL revealed at IBM event. Sony Licenses POWER..

[cthellis42]

Parties have been relatively unsure of the "who-goes-what-where," and certainly of the exact nature of licensing agreements between them. Sony also has PC lines and all sorts of set-top hardware where other Power-derived chips may end up, if they don't consider the first CELL implementation ready enough (or able to be produced in enough volume with PS3-et-al requirements needing to be filled first, or is not yet as cost efficient, or...) Offhand it just asks a few questions while answering none--there's too much vagueness. It'd be rather like wondering if ATi cancelled the Xbox2's GPU because they devoted a session to talking only about R420, or Microsoft canning Longhorn because they were talking about NXA. I mean, all hardware and software is intrinsically connected with direct paths, right?

For the most part, we should be building commentary off what is said, not assumptions through what is omitted while selectively quoting... We get plenty-enough rumors as it is.

 

[Vince]

Also I thought since CELL was a joint venture between Sony, IBM and Toshiba that Sony wouldn't need to actually licence a key eliment in that architecture from IBM.

I figure it would be akin to Sony and MIPS. I've read that Sony holds rights (not sure if joint) to the Cell architecture and, contrary to DM, don't have to pay for that or manipulate it themselves. I dunno, good question.

 

[zidane1strife]

Erm, please tell me that your not suggesting that Deadmeat is an alternate account of mine..........

Nope. Maybe it's some people who frequents the 3d boards, or general discussion, and use these accounts while on the console areas...

 

[Deadmeat]

...

I figure it would be akin to Sony and MIPS.

Exactly. MIPS would have gotten a cut everytime SCEI sold EE to 3rd party, because EE was built on top of R5900.

I've read that Sony holds rights (not sure if joint) to the Cell architecture and, contrary to DM, don't have to pay for that or manipulate it themselves. I dunno, good question.

You don't know, but I already answered that question.

IBM = CELL licensor.
SCEI = CELL primary licensee who bought the right to sublicense for $400 million.

Why is this so hard to understand????

 

[Deadmeat]

..

A similar business practice already exists.

1. IMG issues the primary PVR MBX license to ARM.
2. In turn, ARM sublicenses PVR MBX to ARM licensee.
3. Revenue brought in from Step 2 is shared between IMG and ARM.

Why does this work? Because ARM could market MBX better than IMG ever could.

 

[Vince]

Re: ...

First of all, Deadmeat, you don't know what the agreement between them entails. So to say they get a per IC "cut" is remarkably ignorant... guessing this isn't a new position we're in.

You don't know, but I already answered that question.

IBM = CELL licensor.
SCEI = CELL primary licensee who bought the right to sublicense for $400 million.

Why is this so hard to understand????

Bullshit. Prove it. I want to see someone competent state this.

Link[/url]]The architecture of the Cell chip may also be licensed to other computer manufacturers in the future, including IBM which may use a version of the Cell chip in its next generation of servers.

 

[Deadmeat]

...

http://news.com.com/2100-1006_3-5182742.html

The Blue Gene/L supercomputer, due next year from IBM, will incorporate very large numbers of relatively low-speed, but less power-hungry, processors. A Blue Gene/L concept system with 32 nodes was shown at the New York event. With processors running at only 500MHz, it registered a performance of 128 gigaflops, according to IBM.

Huh, it takes 64 processors(each node chip packs 2 CPUS) to reach 128 GFLOPS? And IBM is going to sell it as a personal supercomputer next year???

Things are not looking good for teraflop CELL indeed...

 

[MfA]

There is a lot of overlap between SOCs and CMP processors, Cell could be an initial testbed for these new Power cores ... or this license could have nothing to do with the PS3 at all.

 

[Brimstone]

Re: ...

http://news.com.com/2100-1006_3-5182742.html

The Blue Gene/L supercomputer, due next year from IBM, will incorporate very large numbers of relatively low-speed, but less power-hungry, processors. A Blue Gene/L concept system with 32 nodes was shown at the New York event. With processors running at only 500MHz, it registered a performance of 128 gigaflops, according to IBM.

Huh, it takes 64 processors(each node chip packs 2 CPUS) to reach 128 GFLOPS? And IBM is going to sell it as a personal supercomputer next year???

Things are not looking good for teraflop CELL indeed...

I highly doubt (its probably impossible) an individual CELL based CPU (MPU?) will hit a Terraflop, but I do think the Playstation 3 will have strong raw performance overall. The performance could stem from several CELL based CPU's working together. If Microsoft is going to have 3 dual core CPU's, nothing is stoping Sony from putting in more than 1 CELL CPU except for cost.

 

[Deadmeat]

...

Well, I figured out why it clocked at only 500 Mhz; it is the same clock speed that first BG/L ran. IBM has not been able to improve on clockspeed ever since.

Since IBM's goal is 5 Watts/GFLOP, this particular personal BG/L was burning ~600 Watts at the peak...

When you set up your PSX3 system, make sure your socket has enough power(600 Watts) rating. And keep enough space from the wall to ensure ventilation, it's going to get really warm....

 

[Deadmeat]

...

If Microsoft is going to have 3 dual core CPU's, nothing is stoping Sony from putting in more than 1 CELL CPU except for cost.

2 physical cores, 4 virtual cores.

 

[freq]

Re: ...

http://news.com.com/2100-1006_3-5182742.html

The Blue Gene/L supercomputer, due next year from IBM, will incorporate very large numbers of relatively low-speed, but less power-hungry, processors. A Blue Gene/L concept system with 32 nodes was shown at the New York event. With processors running at only 500MHz, it registered a performance of 128 gigaflops, according to IBM.

Huh, it takes 64 processors(each node chip packs 2 CPUS) to reach 128 GFLOPS? And IBM is going to sell it as a personal supercomputer next year???

Things are not looking good for teraflop CELL indeed...

Can someone tell me how this idiot hasn't been kicked off for being a troll yet? I mean, he makes up some connection between Power5 and cell that hasn't been made ANYWHERE in any documentation except for the odd badly-reported article, and then he uses it as an "I-told-you-so" inflammatory comment backed up with a bunch of made-up-numbers that are so stupid noone even bothers to take time out of their schedule to point out how assinine they are... And that's just this thread alone!!!

 

[Vince]

Re: ...

Huh, it takes 64 processors(each node chip packs 2 CPUS) to reach 128 GFLOPS? And IBM is going to sell it as a personal supercomputer next year???

Things are not looking good for teraflop CELL indeed...

I'm bored and don't like Deadmeat, so lets have some factual fun with numbers.

BlueGene L is composed of nodes, each of which contains two PowerPC 440 FP2 cores with 2KB of L2, some N amount of shared cache I can't find, and 4MB of L3, a enhanced "double" FPU, a JTAG, processor-to-processor, and Ethernet interface and their associated buffers all within an 11mm^2 IC built using the 130nm process node.

So, if we assume a very simplistic linear shrink to 65nm, we have each node (of two processors) taking up 5.5mm^2.

The 250nm Graphic Synthesizer will provide us a production area viable area bound with it's 270mm^2 size. Which would allow us to embed 49 nodes in the same area.

So, we've managed to embed 49 nodes that contain 98 PowerPC 440 cores, 98 "double" FPUs, 196KB of L2, an amazing 392MB of L2, and a whole bunch of other shit which is redundant 97 times over.

And all we insane, maniacal, optimists want is an IC with 1/24 of those PowerPC cores, 2/3ths that number of FPUs and FXU's, and 1/6th that much in eDRAM in return for marginal gains in logic and 8X in clock offset by SOI, Low-K, lith size and logic tradeoffs.

Now, if you want something truely speculative and on-the-edge, you propose what I did to Pana & Faf the other day for shits and giggles. Those corresponding numbers just keep popping up

 

[Deadmeat]

...

he makes up some connection between Power5 and cell that hasn't been made ANYWHERE in any documentation except for the odd badly-reported article,

http://www.forbes.com/forbes/2002/0415/207_print.html

The project has been run in deep secrecy for a year. James Kahle, IBM's lead architect for the chip, says the Cell design borrowed from IBM's Power4 chip (used in high-power servers) but evolved differently.

You have much to learn..... You and I are on the different plane of understanding..

 

[Deadmeat]

....

all within an 11mm^2 IC built using the 130nm process node.

It's actually 121 mm^2. 11 mm x 11 mm = 121 mm^2

So, if we assume a very simplistic linear shrink to 65nm, we have each node (of two processors) taking up 5.5mm^2.

Try 30 mm^2 intstead...

The 250nm Graphic Synthesizer will provide us a production area viable area bound with it's 270mm^2 size. Which would allow us to embed 49 nodes in the same area.

9 nodes.

So, we've managed to embed 49 nodes that contain 98 PowerPC 440 cores, 98 "double" FPUs, 196KB of L2, an amazing 392MB of L2, and a whole bunch of other shit which is redundant 97 times over.

No wonder why you still dream of teraflop CELL...

 

[Vince]

Re: ...

You have much to learn..... You and I are on the different plane of understanding..

Cockroach...

Sorry, I just watched Scarface. Forgive me.

 

[MfA]

Wow that was a relatively mild correction ... I told you this last time Vince.

Ill repeat, the most up to date info on Bluegene/L is here AFAIK.

The relevant doc is "BlueGene/L Supercomputer Hardware". "BlueGene/L Hardware Architecture Overview" has a piechart showing the percentages the various components take up on the chip.

 

[Vince]

Re: ....

It's actually 121 mm^2. 11 mm x 11 mm = 121 mm^2

Linkified[/url]]The nodes themselves are physically small, with an expected 11.1-mm square die size, allowing for a very high density of processing. TheASIC uses IBM CMOS CU-11 0.13 micron technology and is designed to operate at a target speed of 700 MHz

 

[Deadmeat]

...

http://www.llnl.gov/asci/platforms/bluegene/papers/4kopcsay.pdf
Page 6 of this IBM pdf(11 mm x 11 mm die size spelled out)

Vince, you don't know much. Please don't interfere in the subject you don't understand...

 

[freq]

Re: ...

he makes up some connection between Power5 and cell that hasn't been made ANYWHERE in any documentation except for the odd badly-reported article,

http://www.forbes.com/forbes/2002/0415/207_print.html

The project has been run in deep secrecy for a year. James Kahle, IBM's lead architect for the chip, says the Cell design borrowed from IBM's Power4 chip (used in high-power servers) but evolved differently.

You have much to learn..... You and I are on the different plane of understanding..

Yeah... mine's called "reality", where "Borrowed from an architecture but evolved differently from" does NOT mean "Identical to and can be commonly exchanged for each other in regular conversation and in quoting specs".

Moron. That's what you call a made-up connection.