USB-A Superspeed is still as fast?
Next Generation Hardware Speculation with a Technical Spin [post E3 2019, pre GDC 2020] [XBSX, PS5]
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USB-A Superspeed is still as fast?
cheapchips
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USB C can go up to 20 GB/s. Type A is 10gb/s, as far as I can tell, unless it can use dual channel?
Context for those unable to view twitter/tweets,
Following this snafu, I was able to confirm with several insiders about the actual ports on the current early iterations of the hardware. Keep in mind, these may not be final and are subject to change but do come from multiple people familiar with the hardware.
As it stands right now, the series X features, on the back of the hardware, two USB-A ports (of the SuperSpeed variety), ethernet, a single HDMI port, optical audio, and a power connection. There is also another port on the back that may be used for debugging but there wasn’t an agreement on the nature of its functionality. The image at the top of this post shows a basic outline of how those ports appear on the actual hardware.
Also, on the back of the device are openings for air intake as well; all of the ports are located on the lower half of the hardware. Keep in mind, there is also a USB-A port on the front of the console but for now, it looks like Microsoft is sticking with the older USB style port.
Miniature Kaiju
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TBP, not TDP. Very different metric.
cheapchips
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Wasn't that just Brad's speculation?
D
Deleted member 13524
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Looking at DF's comparison between the SoCs you'll see that Scorpio's Jaguars are larger than Neo's by a substantial amount, but it could just be Microsoft adopting more transistors optimised for clocks and Sony using ones optimised for density.
Microsoft did say they did some customization on the CPU to help with the bottleneck improving drawcall performance. The difference could be significant.
yes, I understand this...what I don’t understand is why PS3 and the first revision of Pro required the more heavy duty power lead when XSX will consume more power yet only need a standard figure of 8.
I was expecting a kettle lead but I guess it’s just how it is!? Sorry if it’s a dumb question, just seemed odd to me.
It's varying by country and voltage. Having a universal 100v to 240v PSU is more difficult to meet all requirements everywhere from a single design. It's not necessarily just the connector versus the wattage.
Technically if they have different PSU models for US, EU, and Japan, I think they can use the small connector and meet individual country electical code.
Or maybe the laws changed.
There may have been different implementation choices as far as the low-level libraries for the cores, but the microrarchitectures of the CPU itself was mostly unchanged.
Microsoft did note that the page table translation hardware for their Jaguar implementation expanded the number of entries and cached more intermediate translations between different virtual memory spaces.
This seems to have borrowed from the improvements AMD's TLBs had been making since the initial Jaguars, and likely mattered more for Microsoft because its system is reliant on a heavily virtualized setup.
While not a major overhaul, it's actually more of a change than usual given how critical the core portion is, which usually makes changes more costly. It's possible this was peripheral enough and AMD was able to take advantage of some kind of space savings to keep the impact on the rest of the CPU block minimal.
Frenetic Pony
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Is this a monolothic die? Kind of surprising if they're not using chiplets, by the time the consoles ship they could include an infinity fabric version with PCI Express 5.0/CXL, more than enough bandwidth and low enough latency not to care versus higher yield.
As for what could be on there, that's much harder to calculate. Since it's an APU we'll need to go off the new 4000 series APUs that are coming up as an exemplar. 8 cores with a basically non existent GPU size hits 150mm squared according to Anandtech. From comparisons between the 5500 and 5700 we can see a full 2 shader engine block seems to take up about 100mm squared. From that we only get 2 big shader blocks from 200mm, assuming the 7nm+ density advantage gets taken up by raytracing hardware. Remember that the compute units on the 4000 should take up almost no die size, so all the other functional blocks are still being included from that 150mm die, plus more or less 200mm die size from RDNA 2, and you get the Scarlett die.
So 56cus looks like a false rumor, meaning the 36cu for PS5 could just as easily be false. Of course the 56 thing never made a lot of sense, from overclocked 5700xt we can see the chip is clearly hitting a bandwidth bottleneck very, very quickly. To the point where if the new "extra WGP per SE" is RDNA 2 standard, it'd need both 16gbps GDDR6 and improved delta color compression just to avoid bandwidth bottlenecks on bigger chips meant to run at higher resolutions. Going by AMDs designs 56 would be a 64cu/32 WGP with a few disabled for salvage. At 8 WGP per Se you'd get ridiculous bandwidth bound unless you had nonexistent 20gbps+ GDDR6.
I think at this point we can assume the "leak" was probably someone that saw the earlier rumor of a 64cu "Big Navi" which never sounded right to begin with and then decided to pull a clever prank, or at least that's my bet. If the die size is accurate, even for the upper limit, I'd still go with a 48cu Xs. Basically an RDNA 2 6700, maybe salvage with a CU or 2 disabled maybe not depending on yield. That works out much better for the die size as well.
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anexanhume
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Precisely. The 5700M, which has the same number of CUs, probably similar clocks, but the wider memory bus of its 5700 parents, has a TDP of 120W. Linearly scaling the CUs from there still only gets you to 190W. With the CPU portion probably less than or equal to 35W, there's probably a little clock scaling room to sit around 250W TDP for the die.
I used a different reference from anybody else (package pitch), and ended up at 388 mm2. Big margin of error regardless.
anexanhume
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You want to use the larger reference point you can because a fixed number of pixel errors will hurt you the least. Package pitch is probably tough for these due to the size of the grid.
All this post is missing is "you're not getting $600 dollar RTX 2080 performance in a $400 console".
Yeah but there are rows of 4 all around so measuring 1.2 (3x 0.40) isn't that much worse than the 1.6 length of the 0603 packages. The pitch of solder pads however allows to use the center easily, since the fuzzy focus is symmetrical.
Okay, the res/cap arrays are almost assured to be spaced based on the underlying BGA pitch to fit with vias (so either 0.40 or 0.50 quantized) and it seems to be 0.40. The space between each little chip in a string is spaced exactly 2.4mm or 2.5mm.
Measuring each string of 7 or 10 as close to the chip,as possible the image has a slight vertical stretch. I averaged the string on each side, with a tiny difference.
Vertical 22.231 pix/mm
Horizontal 21.758 pix/mm
So I get a rather precise 350 mm2.
No that makes no sense. But that's what I have. Maybe it shifts 0.1 per chip to align with a 0.50 bga and fan out. So 2.5 per chip means... 380 mm2.
Measuring each string of 7 or 10 as close to the chip,as possible the image has a slight vertical stretch. I averaged the string on each side, with a tiny difference.
Vertical 22.231 pix/mm
Horizontal 21.758 pix/mm
So I get a rather precise 350 mm2.
No that makes no sense. But that's what I have. Maybe it shifts 0.1 per chip to align with a 0.50 bga and fan out. So 2.5 per chip means... 380 mm2.
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