Next Generation Hardware Speculation with a Technical Spin [2019]

Discussion in 'Console Technology' started by AlBran, Dec 31, 2018.

  1. Jay

    Jay
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    That would be really interesting to see.
    Would have to take into account Lockhart and azure apu usage.
    Something I should've asked for earlier
     
  2. Metal_Spirit

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    As you stated:

    Anaconda
    48 cu @ 1.15Ghz = 7.07 TF 2 disabled * 2 chiplets = 14.14 TF

    So, you are using 96 CUs at 1.15 Ghz to get 14.14 Tflops

    I guess the important thing here is:

    Which one is cheaper? Your solution or:

    60 CU @1850 = 14 .28 Tflops

    This solution kills 4 CU, you kill 8.

    This solution is one GPU, yours is two.

    This solution is hotter. Your solution uses more power.

    Now, with Navi expected to go above 2 Ghz, and Gonzalo working at 1.8 GHz, I do not see thermals as a real problem on Navi... Might be wrong though!
     
  3. iroboto

    iroboto Daft Funk
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    The answer may depend fully on the yields. The higher the clock speed the less yield you're going to get, CUs are just one factor. When you are approaching desktop speeds, the cost savings of running a weaker chip should be melted away.

    This is likely why Scorpio came in 1 year later despite being the same node as 4Pro. They ran 40 CUs at higher clock speed vs many CUs at lower clock speed which was against what we thought was possible, they came in 300Mhz higher than the expectation. The Hovis method helped I'm sure, but likely they really were waiting for the 16nm process to improve better yields at that clock speed to create an achievable price point.
     
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  4. liem107

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    There would be no GPU interconnect because everything would go through the IO chip.. I mean adding second GPU chiplet would just appear as more CU in one GPU I guess? There would be no AFR rendering beacause everything would appear as one GPU... I guess?
     
  5. Metal_Spirit

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    That is why I do not believe in 60 CUS, but 56. At 12.9 tflops!
     
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  6. iroboto

    iroboto Daft Funk
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    I also like higher clock speeds because the whole pipeline speeds up. If you go slow and wide, everything else needs to go wide as well. Lots of costs there and I'm not sure what the savings will be on a chip that large. They need the silicon space for things like ray tracing and other items.
     
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  7. Jay

    Jay
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    Wouldn't mine be killing 4 cu's in total.
    Although I did also say that may be able to have all fully enabled in Anaconda and Lockhart uses ones that needed to have some disabled.

    1.8Ghz in console and cloud sounds high to me, but as you say maybe it's not.
    If running so high isn't a problem then maybe my chiplet frequency examples was way to low?

    Remember you would also have to factor in cooling into cost
     
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  8. Metal_Spirit

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    Yes... I totally agree!
     
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  9. Jay

    Jay
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    Depending on how RT is implemented, having lots of cu's may actually be a lot better.
    I kept frequency low for heat reasons etc. But sounds like could be faster.
     
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  10. Metal_Spirit

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    Oh sorry... I forgot. You were talking about binning GPUs.
     
  11. iroboto

    iroboto Daft Funk
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    I think RT cores are separated from the CUs, the CUs only do the work after the intersections are identified.
    If this is the case, more CUs would be great for a lot of parallel and coherent work, but ray tracing intersections tend to be incoherent, I would suspect that having faster clock speed will help more in these scenarios.
     
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  12. Jay

    Jay
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    Yea, binning for defects more than speed as you can run everything a lot slower which also means more usable dies.

    Lockhart gets the dies that needed cu's disabling.
    I included some in Anaconda as I have no idea regarding yeild output. Just throwing ideas out and wanting input from everyone

    Worth noting I would be surprised if it was chiplet based.
     
    #2092 Jay, May 15, 2019
    Last edited: May 15, 2019
  13. Metal_Spirit

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    It might... But i have serious doubts about that!
    If rumours talked about future navis using multi gpu, I could believe that it was worth it, but there is nothing on the horizon or even mentioned about it beeing used.
     
  14. AlBran

    AlBran Ferro-Fibrous
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    Save the clock boost for mid gen. :p

    There is some merit to going wide in the sense that they can just boost things later in the generation. At the start they’ll be somewhat more concerned with yields, and both a modest clock and wide design can serve that (obviously needs balancing so we aren’t making a small pizza sized chip).
     
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  15. AlBran

    AlBran Ferro-Fibrous
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    The interconnect between the chiplets and IO die is what I mean. you still need IO perimeter on there. e.g. the HSIO link between 360 mother-daughter dies.

    Things may matter in terms of where the GPU’s last level cache is? Hence wondering about putting that on a hypothetical IO die.

    Anyways, I feel like we’re all straying far away from a console with all this chipper stuff.

    Edit: thanks autocorrect. Chipper = chiplet
     
    #2095 AlBran, May 15, 2019
    Last edited: May 15, 2019
  16. iroboto

    iroboto Daft Funk
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    eh ;)
    mid gen refresh came with both a CU increase and a clockspeed increase ;)
     
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  17. AlBran

    AlBran Ferro-Fibrous
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    Yeaaah, but the situation surrounding yield & node improvements may be very different (28nm to 16nmFF vs 7nmFF to EUV 5nm).
     
  18. iroboto

    iroboto Daft Funk
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    for sure ;) 5nm doesn't seem all that plausible for a big upgrade ;) go for dual GPUs now!
     
  19. Adonisds

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    For the X1X CPU, Microsoft did some changes to the architecture. Do you think they will do the same for the next gen or will they use stock Zen 2?
     
  20. BRiT

    BRiT (╯°□°)╯
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    Depends, did AMD already integrate MS's X1X Jaguar tweaks in Zen2?
     
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