Interestingly the revised Apple TV 3,2 has what appears to be a shrunk version of the 32 nm A5 chip, now only measuring 6 x 6 mm.
Next-Gen iPhone & iPhone Nano Speculation
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ltcommander.data
Regular
It makes sense since the A5X uses external DRAM on the PCB rather than the stacked DRAM of the A5, which would have necessitated larger internal changes.
The originally speculated die-shrunk A5X was thought to be a prime candidate for the next gen Retina iPad Mini, which would have left it under-powered and 2 SoC generations behind the next gen iPad instead of the current 1 generation separation. Since the Apple TV doesn't use the A5X, this should make a 28nm A6X much more likely for the Retina iPad Mini.
Given the age of the A5, it's hard to see Apple releasing any completely new products based on the 28nm A5. It could go into silent refreshes of existing products. But if not, it would be a very small production run being used only in the Apple TV, which doesn't seem cost efficient.
The most interesting question is of course whether it's 28nm TSMC or Samsung.
No idea frankly, but I'd expect a step by step transition to be honest. New SoCs possibly on 28nm/TSMC and existing SoC shrinks to 28nm still at Samsung.
I think iPad mini is supposedly to be cheap. Retina display is not cheap.
Of course, it's not impossible that Apple may decide to create two versions of iPad mini, and phasing out the old iPad 2 at the same time.
I think if Apple can get an adequate supply of IGZO display for iPad mini, it's possible to make a retina iPad mini with reasonable weight. Though, "adequate supply" is the keyword here.
ltcommander.data
Regular
Going with a new SoC design on a new process while interacting with a foundry team you've never worked with before seems pretty aggressive. Some form of tick-tock like Intel, going with an existing design on a new process might provide a smoother transition to TSMC.
I think the broader question is whether Apple wants to switch to a 6 month design cycle for the iPad/iPad Mini. If Apple needs to launch a refresh in the spring, then it seems unlikely that the technology will be ready for a retina iPad Mini. In that case they'll probably just go with an A6 and a laminated full gamut IPS display with improved contrast. A fall iPad Mini, whether as the subsequent 6 month refresh or as the normal yearly release, is much more likely to be retina.
Personally, I don't see the need for a 6 month release cycle since there isn't likely to be major hardware improvements in that timeframe. Apple should just get back to more aggressive software release cycles as a means of refreshing the platform and adding new features. For iOS 4 they released 3 minor updates whereas iOS 5 and so far iOS 6 have only received 1.
The risk might be bigger to go with a new SoC design to 28nm/TSMC than at 28nm/Samsung, but either way there's always some risk there with a new design on a yet untouched process wherever and no I wouldn't suggest that a new SoC design would still be on 32nm/Samsung.
***edit: note "suggest" != "know".
Yes, I agree that Apple shouldn't do a 6 month product cycle, though iPad mini is a special case as it's kind of a first generation product. However, if Apple can't make a retina iPad mini light enough while keeping the battery life, there's indeed no point making it.
anexanhume
Veteran
Yes, if there's any good spec indication, it's that. I've never seen a battery life number quote go down for an iOS device.
So going back to the smaller A5 in the silently refreshed Apple TV - where did they get the 6x6 die size from? Macrumors gives no source for that information, as if it was obvious from their board teardown, which it obviously isn't - you need a chip teardown to know the die size of any chip that doesn't use a flipchip package, and Macrumors obviously isn't going to do that themselves.
If I assume the NAND package is the same size as in the iPad Mini, then I get a package size about 15-20% smaller than the 32nm A5. This implies a slight reduction in package size (equivalent as 14x14 to 12x12 but IIRC those aren't the actual numbers at all) which implies nearly nothing about the die size of the chip - in fact they might even have reduced the package size without changing the chip!
Now if we assume they had another source giving them the die size (unlikely and even less likely to be reliable) then 36mm2 means they probably couldn't fit a 64-bit memory bus (32-bit LPDDR3 or just lower bandwidth?) and it'd be a hell of a shrink, even if TSMC did have a higher density process than Samsung. I suspect they could only achieve that die size by also removing some other stuff (e.g. second CPU core that was already disabled in the Apple TV). Honestly I think the die size is bullshit but it'd be very interesting if it wasn't.
If I assume the NAND package is the same size as in the iPad Mini, then I get a package size about 15-20% smaller than the 32nm A5. This implies a slight reduction in package size (equivalent as 14x14 to 12x12 but IIRC those aren't the actual numbers at all) which implies nearly nothing about the die size of the chip - in fact they might even have reduced the package size without changing the chip!
Now if we assume they had another source giving them the die size (unlikely and even less likely to be reliable) then 36mm2 means they probably couldn't fit a 64-bit memory bus (32-bit LPDDR3 or just lower bandwidth?) and it'd be a hell of a shrink, even if TSMC did have a higher density process than Samsung. I suspect they could only achieve that die size by also removing some other stuff (e.g. second CPU core that was already disabled in the Apple TV). Honestly I think the die size is bullshit but it'd be very interesting if it wasn't.
anexanhume
Veteran
This is what I've been assuming ever since they quoted the numbers they did. I don't see any other way to get there.
Removing a CPU core would barely make a dent towards that endpoint. What would that save them, 1-2mm^2 at most? They'd have to do other things like cut down L2 cache, maybe remove some phone only interfaces and processing (anything camera related?) and probably cut the GPU down too (SGX543MP1).. at some point it becomes pretty silly for Apple to call this "A5" still. They're not really in this habit of making major variations that have the same name.
I think someone just erroneously thought that reduction in package size had a 1:1 correlation to reduction in die size and the tech media is ignorantly running with it. It could very well be the same chip in that package.
I think someone just erroneously thought that reduction in package size had a 1:1 correlation to reduction in die size and the tech media is ignorantly running with it. It could very well be the same chip in that package.
Doesn't Apple have an non lossy compression format?
I suspect 1xA9/512KB L2 and a 32-bit LPDDR2-1066 interface might be enough (remember the original iPad 2's A5 used 64-bit LPDDR2-533 iirc) if they had a much more aggressive area-optimised synthesis. At that point it's still close enough to the original A5 in my opinion.
Also keep in mind that based on public die shots, the A5 32nm's A9s (excluding L2) are actually slightly bigger than the OMAP4's A9s - and that's 32nm vs 45nm! And the same may or may not be true of the rest of the SoC. So it's really impossible to predict die size without knowing Apple's synthesis strategy.
I agree that seems most likely, although the claimed reduction in die size is actually a higher percentage than the reduction in package size (considering my <20% estimate based on the NAND package size). The simplest way they could get to a 6x6 die size is to see a 12x12 package and assume the actual die is half in both directions - but surely nobody is THAT ignorant, right? :|
ltcommander.data
Regular
The original A5 used 64-bit LPDDR2-800. There're going to be behind in memory bandwidth with 32-bit LPDDR2-1066 although perhaps they don't really need it if they are only going single-core CPU and GPU.
For all we know they could have just taken a knife and torn the SoC off the PCB and a 6x6 bit of silicon was all that's left.
Did they actually move the RAM off package? There's usually silkscreening on all four sides of the A5 with the RAM listing on one side, but this chip only has silkscreening on two sides. The chip to the left of the A5 might be the RAM? That might provide the marginal package size savings while the underlying die is still 32nm. I wonder why Apple would go to the trouble of redesigning the Apple TV to move the RAM off package though?
Admittedly we don't know Apple's nomenclature, but it does seem strange that if there wasn't a die shrink, just a repackage, that it would require a change in model number from S5L8942 to S5L8947 including references in iOS. Even with half the functionality, the Apple TV's previous A5 kept the same S5L8942 number as the full 32nm A5 both on the hardware silkscreen and in iOS references.
Is it possible that A5 supported DDR3 all along? Although that seems strange it's not that out there since plenty of other mobile SoCs support it, and it might not be a huge addition in logic and verification to support both it and LPDDR2. Or if they really did change the chip this could have been one of the changes.
DDR3 would be cheaper and easier to source, and since this is a set-top device power consumption is less critical. Last I looked, non-PoP LPDDR2 is a lot harder to find than PoP and Apple would want to save supply for their tablets with 128-bit memory interfaces.
ltcommander.data
Regular
http://www.chipworks.com/blog/techn...side-the-latest-apple-a5-from-a-new-apple-tv/
They are still working on figuring out the process node, but Chipworks is confirming a shrink with a 6.1x6.2mm die on a Samsung process. They are also expecting design changes given the small die size as this thread has been discussing. Off package DRAM has also been confirmed although I can't find a product listing for Elpida B4432BABH whether it is DDR3 or not.
EDIT:
http://www.elpida.com/en/products/pndecoder/index.html
I can't find the specific part, but Elpida's nomenclature with suggests it's 512MB of LPDDR2-1066.
They are still working on figuring out the process node, but Chipworks is confirming a shrink with a 6.1x6.2mm die on a Samsung process. They are also expecting design changes given the small die size as this thread has been discussing. Off package DRAM has also been confirmed although I can't find a product listing for Elpida B4432BABH whether it is DDR3 or not.
EDIT:
http://www.elpida.com/en/products/pndecoder/index.html
I can't find the specific part, but Elpida's nomenclature with suggests it's 512MB of LPDDR2-1066.
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