Next-Gen iPhone & iPhone Nano Speculation

[anexanhume]

Hmmm well IMO if you have in total 6 clusters power gate 5 of them I'd still figure that at least one quad TMU would have to be active, which makes the gain against a 2 USC + 4 TMU active scenario rather negligable as you say. Unless of course you can turn off part of each quad TMU also, but they wouldn't then state that 2 USC share a texture pipeline at a time.

Found a little more description on the technology used:

http://blog.imgtec.com/powervr/new-powervr-series6xt-gpus-go-rogue-ces-2014

Moreover, the PowerGearing G6XT advanced power management technology provides the means for PowerVR Series6XT GPUs to offer more for less: more performance for lower power, when compared to previous generation cores. PowerGearing G6XT is a Series6XT-specific implementation of our advanced PowerGearing techniques and includes a combination of automatically enabling clock gating, enabling/disabling power to clusters, and intelligently using the Microkernel firmware to offer lower latency workload feedback into DVFS and power management decision process.

What of this do we think was present in the initial Rogue cores vs. new to XT? I'm guessing the DVFS stuff is new since it talks about improving the existing process.

 

[Ailuros]

Well I was hoping by now that one of the boys would step in and shed some light on that stuff, but we should cut them some slack. It was only recently when they decided to give a somewhat more extensive description of ALUs. So it's one step at a time

 

[Rys]

Found a little more description on the technology used:

http://blog.imgtec.com/powervr/new-powervr-series6xt-gpus-go-rogue-ces-2014

What of this do we think was present in the initial Rogue cores vs. new to XT? I'm guessing the DVFS stuff is new since it talks about improving the existing process.

It's new for 6XT, based on things we learned during integrations of 6 with customers. There's a whole bunch of changes in there, the better power management being one of them.

If you think about how we've scaled the architecture, the top level view of how we'd approach DVFS in the core comes out. The single USC parts to one side, we scale the architecture up pairs of USCs at a time (there are no 3 or 5 USC parts). So it's that granularity that the power management works at (at least for management of the shader core and associated texture hardware).

 

[anexanhume]

It's new for 6XT, based on things we learned during integrations of 6 with customers. There's a whole bunch of changes in there, the better power management being one of them.

If you think about how we've scaled the architecture, the top level view of how we'd approach DVFS in the core comes out. The single USC parts to one side, we scale the architecture up pairs of USCs at a time (there are no 3 or 5 USC parts). So it's that granularity that the power management works at (at least for management of the shader core and associated texture hardware).

Thanks for the answer. Not trying to be obtuse, just wanting to clarify my original question here to make sure I understand the process. You're saying the DVFS stuff is new, but not necessarily what things are de-clocked and power-gated and how (X vs. original Rogue)?

 

[Rys]

We could obviously support DVFS in 6, but there's new hardware to do it better in 6XT (most of DVFS is software).

So in terms of controlling things at the block level, it's largely the same high-level view of things as with 6, because it's the same base architecture, but the details are different.

 

[mavere]

Supposed logic board of iPhone 6.

Using the SIM slot's features to compare against the 5s board and its A7, the A8 seems to be roughly the same size (~5% smaller by my measurements). At very least, I think this precludes Apple just sticking the A7 on a smaller process and calling it a day.

 

[Ailuros]

* Is A8 manufactured on 20SoC as rumored?
* If yes at the same transistor density as under 28nm Samsung?

I don't think the answer is positive for the 2nd question. If A8 should be at 95nm roughly then it would be dumbest shrink ever.

 

[Helmore]

Supposed logic board of iPhone 6.

Using the SIM slot's features to compare against the 5s board and its A7, the A8 seems to be roughly the same size (~5% smaller by my measurements). At very least, I think this precludes Apple just sticking the A7 on a smaller process and calling it a day.

You don't compare die size based on package size. Haswell and Broadwell will be sold in the same package, that doesn't mean they'll be the same die size.

 

[mavere]

And yet in past iPhones the package footprint is essentially die footprint (for dramatic example, see the 2 AppleTV A5 revisions). I doubt that Apple has changed or would take up extra space on a narrow PCB just for fun.

 

[Helmore]

Then what about the RAM chips that are stacked in the package? How do you account for their size and how they're connected to the SoC die?

 

[mavere]

* Is A8 manufactured on 20SoC as rumored?
* If yes at the same transistor density as under 28nm Samsung?

I don't think the answer is positive for the 2nd question. If A8 should be at 95nm roughly then it would be dumbest shrink ever.

Aren't TSMC 28HPM and Samsung 28HKMG on equal competitive footing? If so, TSMC claims ~1.9x transistor density improvement over 28HPM, and my point above was that Apple would use that large amount of extra transistors to do Something Interesting(TM).

Edit: And if this isn't 20SoC as rumored, then I'm at lost as to who's buying all those 20nm wafers TSMC claims it will sell in Q3 & Q4 and who's footing the bills for the rapid (relative to past nodes) production ramp up.

 

[mavere]

Then what about the RAM chips that are stacked in the package? How do you account for their size and how they're connected to the SoC die?

The overhead there take up slivers at the edge. Are you suggesting that their PoP design constraints have changed somehow?

 

[Ailuros]

Aren't TSMC 28HPM and Samsung 28HKMG on equal competitive footing?

Are they? (honest question). Samsung was never known up until now to have the best processes compared to others and 28HPm TSMC has quite a few benefits compared to 28LP TSMC.

If so, TSMC claims ~1.9x transistor density improvement over 28HPM, and my point above was that Apple would use that large amount of extra transistors to do Something Interesting(TM).

And here again the original sentence I answered to:

At very least, I think this precludes Apple just sticking the A7 on a smaller process and calling it a day.

Just sticking A7 on 20SoC and calling it a day sounds to me like a quick and clean die shrink. If you meant something else it's phrased somewhat awkward. A hypothetical die shrink wouldn't obviously account in just a 5% reduction from 28nm-whatever to 20SoC TSMC.

Edit: And if this isn't 20SoC as rumored, then I'm at lost as to who's buying all those 20nm wafers TSMC claims it will sell in Q3 & Q4 and who's footing the bills for the rapid (relative to past nodes) production ramp up.

Well it doesn't seem that we disagree at all; I just found the 5% die area reduction along with the simple die shrink notion a bit strange. As I said if it would be the case it would be quite a dumb die shrink

 

[Alexko]

You're both saying exactly the same thing and apparently disagreeing about it.

 

[Ailuros]

You're both saying exactly the same thing and apparently disagreeing about it.

No disagreement at all. Now that I know what he meant I know that we agree after all.

 

[iMacmatician]

Supposed logic board of iPhone 6.

Here is a different logic board of what may be the rumored 5.5" iPhone.

 

[anexanhume]

Another curiosity - it appears either the A8 has fewer die pads than A7, they decreased the pad pitch, or both. The resolution makes it very difficult to tell if the pitch has become finer, but I can't rule it out either.

(A7 pads pasted above and to the right of A8).

 

[PawKRK]

Probably memory is only on A8 package. It will take less space on pcb. It make sense, since apple put A8 assemble (stack memory) orders into 3 providers. Both iPhone and iPad chips seem to have stacked memory.

 

[anexanhume]

Probably memory is only on A8 package. It will take less space on pcb. It make sense, since apple put A8 assemble (stack memory) orders into 3 providers. Both iPhone and iPad chips seem to have stacked memory.

All iPhones have had PoP memory, and the pictured A7 is from the iPhone 5S, not the iPad that has off-chip memory.

 

[Ailuros]

Some sort of indirect prelude for the upcoming iPhone generation? http://www.anandtech.com/show/8414/a-month-with-the-iphone-5s

Nice work nonetheless and Joshua seems on a roll with excellent writeups