A lot of things affect transistor density, many of them balancing. If the processes are targeted at the same niche, results from different foundries, at similar process nodes, have been surprisingly close considering just how many variables there are.
Simply principles of physics creating more common solutions. TSMC doesn't even have options at the 20nm node.
My prediction is that in all likelyhood the billion transistors in the A7 aren't partitioned just as in the A6, but that a greater portion of transistors are in highly regular (or otherwise intrinsically more dense) structures. Does that seem unlikely?
Not at all unlikely. Several members have pointed out some big transistor spending blocks potentially.
My potential counterpoint - did Apple creating the M7 move anything off of the A7 that was in the A6? I've even heard people speculate that the 1 billion is across A7 and M7, even though it was clearly on the A7 slide before they even introduced M7.
My feeling is that they have dedicated more die area to CPU than GPU. Some are suggesting that they have gone quad core, that would be a doubling right there (discounting the die shrink). Even if not, then they have used 64-bit CPU, which probably comes with an increase size.
The stated graphics performance, whilst clearly acceptable to Apple, implies a quite conservative Rogue implementation, which again might point towards die size limitations.
Any feeling that the high transistor count might be related to a big increase in my chip memory, given that memory is highly dense.
..edit, I see that's already been mentioned.
My question is whether or not they did a paradigm shift on logic density/circuit block approach. Lot of people have pointed out to me how much less dense the cortex A9 cores were on the A5 compared to other solutions like Tegra 2.
Wasn't the ongoing speculation for some time now that even when Apple start shifting to another fab, that the logistics would be such that they'd have to continue to dual source ?Perhaps my oversimplified conclusion from that was that they'd be getting the same soc from multiple manufacturers. For what people are saying here, it wouldn't be possible for Apple to state an soc size if it was coming from multiple sources.
TSMC is not part of the GloFo/Samsung/UMC foundry alliance, making me think the processes are less likely directly portable. My guess is that if they are indeed sourcing TSMC, that's why Apple isn't providing 5s pre-orders. They anticipate smaller availability. Of course, maybe it's the new fingerprint sensor or CMOS image sensor causing that too.
Is Hydra possibly the "MP" part of a multi-core implementation. I'm certain I've read that SGX544 is different from SGX544MP1 (the implication being that the MP circuitry brings more than just inter core glue).
After having it explained to me, that's my basic interpretation too.
True, that's why I didn't give it as the only example. It is pretty close to being a SoC though, as it's much more than just a CPU, GPU and SRAM on a single chip. It was all just meant as an example of showing that 1 billion transistors in 102 mm² isn't that unusual. The unusual part is Apple claiming that the A7 SoC has double the transistors of A6, or maybe we misunderstood Apple and they were comparing to something else.
Schiller made two claims. He verbally said twice the transistors. They showed 1 billion on the slide. He's not one to misspeak so I believe what he said.
Doesn't Samsung use a gate first approach on their 28nm node, which they trumpet as allowing higher densities, because of less restrictive design rules, apparently at the expense of yield %, compared to gate last. Given that everybody is moving to gate last @20nm, this supposed density advantage can't be that great vs the other benefits of gate last. Come on Chipworks, this wait is killing me
Yes, they do gate first. Interestingly, they're claiming a gate density increase almost on par with the full node transition from 45nm to 32nm in
this PDF. Looks like it's almost a 33% density improvement. I did not give enough credit. I thought they were doing 20% at best.
Interestingly, the gate density that accompanied TSMC's 28nm
announcement in 2009 is 3900Kgates/mm^2. That's the same claim in the Samsung PDF. TSMC is gate-last.
Maybe the density between foundries really isn't all that different.
