NEC Electronics on Xenos (downspec in dice interconnect bandwidth?)

[pakpassion]

whoa i cant believe even after what dave said you still think there is a downgrade. somehow i feel people are wishing there is one.

 

[Alpha_Spartan]

This thread was a failure.

 

[one]

whoa i cant believe even after what dave said you still think there is a downgrade. somehow i feel people are wishing there is one.

Dave is not the manufacturer of the chip Why not contact NEC Electronics if you believe it's a typo? What NEC is concerned with is only Xenos, not Xbox 360 as a whole system, so it's unlikely that they confused it with the UMA RAM bandwidth.

 

[pakpassion]

Dave is not the manufacturer of the chip Why not contact NEC Electronics if you believe it's a typo? What NEC is concerned with is only Xenos, not Xbox 360 as a whole system, so it's unlikely that they confused it with the UMA RAM bandwidth.

but dave has contacts inside ATI which has manufactured the graphics card with MS. so I dunno why you believe this is not a typo, or is it that you want it to be downspecced

 

[one]

but dave has contacts inside ATI which has manufactured the graphics card with MS. so I dunno why you believe this is not a typo, or is it that you want it to be downspecced

Please read my 1st post in this thread which explains why I don't think it's a typo

Aside from futile exchange like this and "LSI circuit" terminology, even though it can be 22.4GB/s it doesn't necessarily mean the parent die clock was synchronized to 32GB/s and was downclocked. As the article says it uses flip chip which may affect only the bandwidth. Please correct me if this doesn't make sense.

 

[pakpassion]

http://techon.nikkeibp.co.jp/article/NEWS/20051005/109392/?ST=lsi (requires free reg)

Nikkei Tech-on has an article about the exibition by NEC Electronics at PROTEC JAPAN 2005 which was held along with CEATEC JAPAN 2005 at the same venue from Oct. 5. The short article features Xenos.
The article was published at Oct. 5 and when I first saw it I thought it's an error though the picture of the material provided by NEC clearly says it's 22.4GB/sec, not 32GB/s. Then later, a correction was added to the article, So apparently NEC reviewed the article after it's published but the 22.4GB/sec figure stayed unchanged.

Though 22.4GB/s looks enough already, is there any impact of this downspec on game development? Another possible theory is it's just the figure for beta kit which is synchronized to a lower frequency of GPU, but I don't know the exact clockspeed of Xenon beta kit GPU, does anyone know details about this?

first of all that logic doesnt make sense. NEC never said they reviewed the article they only said instead of it being NEC which provided the information, it was Microsoft. NEC only made the EDRam, it didnt make the connection between the EDRam and the ATI Manufactured Chip. Thats all NEC were providing. All Information that NEC do know is about the EDRAm chip, now how fast or how slow its connected to other chips or atleast they dont have the authority to know. so it must be a Mistake from MS as ATI has already said its 32 GB/s. No one from Microsoft was available to comment. right?

 

[one]

first of all that logic doesnt make sense. NEC never said they reviewed the article they only said instead of it being NEC which provided the information, it was Microsoft. NEC only made the EDRam, it didnt make the connection between the EDRam and the ATI Manufactured Chip.

You are wrong. NEC Electronics developed the SiP design and manufactures the daughter die. Then according to Dave, IIRC, ASE does packaging of those 2 dice for MS.

 

[pakpassion]

You are wrong. NEC Electronics developed the SiP design and manufactures the daughter die. Then according to Dave, IIRC, ASE does packaging of those 2 dice for MS.

what you just said goes against what NEC said in correction:


""""Though we first wrote "The work for making them in SiP is done by NEC" in this article by an interview at the event, we were informed by NEC Electronics that it's actually done by Microsoft. The article was changed according to this information."""""

The correction says the SIP is done by Microsoft according to the correction statement. so NEC only manufactured the EDRam (daugher die) it didnt seem to have a part in how fast that daughter die connects to the main GPU.

 

[one]

what you just said goes against what NEC said in correction:


""""Though we first wrote "The work for making them in SiP is done by NEC" in this article by an interview at the event, we were informed by NEC Electronics that it's actually done by Microsoft. The article was changed according to this information."""""

The correction says the SIP is done by Microsoft according to the correction statement. so NEC only manufactured the EDRam (daugher die) it didnt seem to have a part in how fast that daughter die connects to the main GPU.

Eh, perhaps my translation was a bit vague, so if you mistook it sorry. The SiP design per se was developed by NEC which is clear in the first sentence in the article with NEC as the subject in the original text, and it should have been translated like "the actual packaging operations are being done" at MS/ASE. Also, the title of the article is "NEC Electronics Developed SiP of DRAM-Embedded LSI and Graphics LSI for XBOX 360" which is not changed.

 

[pakpassion]

Eh, perhaps my translation was a bit vague, so if you mistook it sorry. The SiP design per se was developed by NEC which is clear in the first sentence in the article with NEC as the subject in the original text, and it should have been translated like "the actual packaging operations are being done" at MS/ASE. Also, the title of the article is "NEC Electronics Developed SiP of DRAM-Embedded LSI and Graphics LSI for XBOX 360" which is not changed.

so the correction is either wrong of Nikkie Japan didnt edit thier Title

 

[one]

so the correction is either wrong of Nikkie Japan didnt edit thier Title

Well it's not like dumb gaming magazine for kids. It's one of the biggest electronics industry papers talking with the chip manufacturers.

 

[pakpassion]

Eh, perhaps my translation was a bit vague, so if you mistook it sorry. The SiP design per se was developed by NEC which is clear in the first sentence in the article with NEC as the subject in the original text, and it should have been translated like "the actual packaging operations are being done" at MS/ASE. Also, the title of the article is "NEC Electronics Developed SiP of DRAM-Embedded LSI and Graphics LSI for XBOX 360" which is not changed.

(System in Package) A complete system packaged in one housing. A SiP contains several ICs (chips) including a microprocessor on a single substrate such as ceramic or laminate. A SiP is really a multichip module (MCM) that contains all the parts of a complete system. The SiP term was first used by Amkor Technology in the late 1990s and not trademarked in order to encourage its use worldwide.

SiP thus doesnt apply to NEC because NEC only designed the EDRAM and no other component of the Xenos. There are innumerable articles about that.

 

[MrSingh]

http://www.ati.com/developer/eg05-xenos-doggett-final.pdf

Slides No. 3 & 4.

So do we still assume NEC is right and one of the Xenos architects is wrong?

 

[darkblu]

The correction says the SIP is done by Microsoft according to the correction statement. so NEC only manufactured the EDRam (daugher die) it didnt seem to have a part in how fast that daughter die connects to the main GPU.

so NEC manufactured the edram die but they don't know what speed it connects to the GPU (regardless of who designed the SIP interconnects)..

jeasus freakin christ.. pakpassion, how old are you?

ok, this discussion passed the point of sanity long time ago (about the time powderkeg invented the 'LSI part of the chip' nonsense)

to all the xbox f*boys posting in this thread trying desperately to disprove the article in any possible half-wit way, here's a multiple choice for you:

a) the number in the article is a typo
b) that's the bw in one direction only (though the edram in this case would likely need to be dual-ported, etc)
c) the edram daughter part was indeed downclocked, the GPU may or may not have been downclocked.

pick one of the above according to your taste and stick to it.
any other explanation you may come up with, dream about, or devise while sitting on the toilet is a product of your wishful thinking. show some freakin maturity, or don't post here (not posting about things you don't understand is also mature). for your own sake.

anyway, that's my last post in this insane thread. have a good night.

 

[one]

SiP thus doesnt apply to NEC because NEC only designed the EDRAM and no other component of the Xenos. There are innumerable articles about that.

So? I have no idea why you stick to that argument about SiP as the bus bandwidth can't be isolated from what's connected.

http://www.ati.com/developer/eg05-xe...gett-final.pdf

Slides No. 3 & 4.

So do we still assume NEC is right and one of the Xenos architects is wrong?

Unless confirmed otherwise by related parties.

 

[pakpassion]

so NEC manufactured the edram die but they don't know what speed it connects to the GPU (regardless of who designed the SIP interconnects)..

jeasus freakin christ.. pakpassion, how old are you?

ok, this discussion passed the point of sanity long time ago (about the time powderkeg invented the 'LSI part of the chip' nonsense)

to all the xbox f*boys posting in this thread trying desperately to disprove the article in any possible half-wit way, here's a multiple choice for you:

a) the number in the article is a typo
b) that's the bw in one direction only (though the edram in this case would likely need to be dual-ported, etc)
c) the edram daughter part was indeed downclocked, the GPU may or may not have been downclocked.

pick one of the above according to your taste and stick to it.
any other explanation you may come up with, dream about, or devise while sitting on the toilet is a product of your wishful thinking. show some freakin maturity, or don't post here (not posting about things you don't understand is also mature). for your own sake.

anyway, that's my last post in this insane thread. have a good night.

well looking at the ATI slides from the Xenos article. it gives ample proof that the article is a typo

 

[scooby_dooby]

deleted

 

[Shifty Geezer]

So do we still assume NEC is right and one of the Xenos architects is wrong?

There's no point assuming anything. We have two conflicting specifications. We have an amount of evidence that we can call upon to consider. Under the weight of evidence it would seem that this 22.4 GB/s figure is a numerical inaccuracy, but cannot be proven either way. So until the machine is out you have the option to believe in one or other figure, or take a totally neutral stance and see what happens. Believing that the interconnect bus is 32 GB/s isn't going to make it 32 GB/s, not the ame wth 22.4 GB/s. The interconnect speed is whatever it is made to be regradless of what people believe it will be.

As there's no way of knowing, short of stealing a few XB360's and dissecting them, all we can do is add more information regards these techs to our knowledge base and see which pieces fit an overall picture best, to aid our best guesses. This NEC news is just as relevant as any other in worth of being considered and one, who is an excellent source of info from Japan, did right to communicate it and let us enjoy are speculative pasttime.

 

[MrSingh]

let's not speculate. let's just say NEC is right. this thread is a waste of time.

 

[Guden Oden]

this thread is a waste of time.

With posts like that, it certainly will be.