pakpassion
Banned
we will wait for Dave has to say about this.
NEC Electronics on Xenos (downspec in dice interconnect bandwidth?)
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- Start date
mckmas8808
Legend
Wow this is getting crazy. We really do need Dave for this one.
Shogmaster
Regular
Hardknock said:With the appropriate GameFaqs headline no doubtKlee seems to be good at those.
Check it out:
http://www.ga-forum.com/showthread.php?t=66521
KLEE is like the Jerry Springer of X360/PS3 news reporting over at GAF. He must really miss his GameFan days.
pakpassion
Banned
Shogmaster said:KLEE is like the Jerry Springer of X360/PS3 news reporting over at GAF. He must really miss his GameFan days.
any Mod able to contact dave? this is getting out of control. needs to be resolved before the sleep cycle is distrupted
mckmas8808
Legend
Shogmaster said:KLEE is like the Jerry Springer of X360/PS3 news reporting over at GAF. He must really miss his GameFan days.
He aight that bad. I've seen worst.
pakpassion
Banned
Article Date: June 26th 2005
Ati is Xbox360 development this funds specially makes the chip development code is " C1 ", the other name " Xenos ", the capacity reaches as high as 512MB, basic frequency 700MHz, has the formidable function.
Xenos used differently to the PC mainstream graph processing chip design, originally will separate the apex coloration (Vertex Shader) (Pexel Shader) scattered with the picture element coloration, changes unified the colouring overhead construction (Unified Shader Architecture) the way constitutes, and matched can provide the stable deposit and withdrawal frequency width, has Z / Stencil Testing, Alpha Blending and the entire screen counter- denticle (FSAA) and so on in processing 10MB inlays the memory (Embedded DRAM), provided the stable high performance graph processing.
Xenos constitutes by two big chips, one for the core processing chip, another is the mix partial graph processing electric circuit and the memory ecDram chip, and by multi- chips module (MCM) the way union is the sole seal. May see in this graph processor seal by the under chart has two chips, port side is the ecDram chip, by NEC the 90nm craft production, the scale is 105000000 transistors, right flank for the core processing chip, produces by the 积电 90nm craft, the scale is 232000000 transistors, between by 32gBps frequency width main line connection.
Xbox360 sells along with November, 2005 Japan approach, this mystical and the formidable main engine more and more approached us.
and they already have a picture of Xenos:
http://www.btbbt.com/Article/UploadFiles/200506/20050626161308980.jpg
1) Why would be downgrade after it was taped out?
2) They have already manufactured the graphics card according to the chip picture, that means the info Dave Got is one OF the Graphics card connection, why would they ever reduce bandwidth?
Ati is Xbox360 development this funds specially makes the chip development code is " C1 ", the other name " Xenos ", the capacity reaches as high as 512MB, basic frequency 700MHz, has the formidable function.
Xenos used differently to the PC mainstream graph processing chip design, originally will separate the apex coloration (Vertex Shader) (Pexel Shader) scattered with the picture element coloration, changes unified the colouring overhead construction (Unified Shader Architecture) the way constitutes, and matched can provide the stable deposit and withdrawal frequency width, has Z / Stencil Testing, Alpha Blending and the entire screen counter- denticle (FSAA) and so on in processing 10MB inlays the memory (Embedded DRAM), provided the stable high performance graph processing.
Xenos constitutes by two big chips, one for the core processing chip, another is the mix partial graph processing electric circuit and the memory ecDram chip, and by multi- chips module (MCM) the way union is the sole seal. May see in this graph processor seal by the under chart has two chips, port side is the ecDram chip, by NEC the 90nm craft production, the scale is 105000000 transistors, right flank for the core processing chip, produces by the 积电 90nm craft, the scale is 232000000 transistors, between by 32gBps frequency width main line connection.
Xbox360 sells along with November, 2005 Japan approach, this mystical and the formidable main engine more and more approached us.
and they already have a picture of Xenos:
http://www.btbbt.com/Article/UploadFiles/200506/20050626161308980.jpg
1) Why would be downgrade after it was taped out?
2) They have already manufactured the graphics card according to the chip picture, that means the info Dave Got is one OF the Graphics card connection, why would they ever reduce bandwidth?
pakpassion
Banned
forgot to post the article link: http://translate.google.com/transla...firefox-a&rls=org.mozilla:en-US:official&sa=N
Panajev2001a
Veteran
mckmas8808 said:
No we DO NOT. Going by ancient definitions for SSI, LSI, VLSI, ULSI as some people were doing here is the problem.
In the industry they indeed use the word LSI as IC or Integrated Circuit before someone using the Wiki starts going nuts.
The likely thing is that the diagram between Xenos and the daughter die is wrong counting only one way bandwidth while you should have separate read and write busses.
pakpassion
Banned
Panajev2001a said:
so can you tell in laymans terms whats wrong with the article, the picture and the whole situation.
pakpassion said:
In that article, NEC is showcasing their SIP that their design to house their embedded DRAM LSI and TMSC graphic LSI.
As it happend, NEC billboard showcasing their SIP, has 22.4 GB/s as the capability of their SIP.
So its either that their SIP couldn't handle the 32 GB/s or they wrote a wrong number on the billboard showcasing the SIP.
The article has been reviewed and corrected by NEC. Now we are just waiting for Dave to comfirm or correct NEC.
So Dave ?
If we are taking the slide literally what would we gather from the pair double ended arrows.
Also, does anyone recall the exact read/write bandwidth in the diagrams between the parent and daughter die? I am heading out so I cannot find it right now but maybe that info could be helpful.
Also, does anyone recall the exact read/write bandwidth in the diagrams between the parent and daughter die? I am heading out so I cannot find it right now but maybe that info could be helpful.
I don't think it's been mentioned, but if we go by the reported CPU frequency we have 2.8 GHz -> 3.2 GHz which is a .875 ratio. If the GPU followed suit the beta kit would have been 437.5 MHz, that multiplied by the 512 bit bus gives you... ~22.4 GB/s.one said:
Whether that means anything or not, I don't know. I rather doubt they scaled the GPU back since ATI were talking about how easily Xenos went to 90nm and how happy they were with its production and that was what gave them (false, it turned out) confidence about the 520.
MechanizedDeath
Regular
Actually, it would be 350MHz. 350Mhz x 64B = 22.4GB/s. PEACE.chachi said:
mckmas8808
Legend
MechanizedDeath said:
Why that makes me really think that it's not true. No way is this possible.
Yeah, I was just about to edit, forgot to divide by 8, d'oh.MechanizedDeath said:
The second part I stand by though, ATI has been all sunshine and gumdrops about Xenos and given how easily leaks find their way to the net from MS confidential documents if there had been a major change like this you think we'd have heard about it already.
