More hits to the heart for the 4 PE's CPU fans (CELL)

[j^aws]

this Wafer is a 10S process and the 10S (90nm),11S (65nm) ,12S (45nm) process (SOI,lowK) developed by STI for the Cell is not a eDRAM process, i think
the eDRAM+logic process is developed by Sony and Toshiba (for the GPU probably) and named CMOS4 (90nm> PSP chip and EE+GS chip), CMOS5 (65nm > PS3 GPU?), CMOS6 (45nm, PS3 GPU evolution) and is not SOI

Good point...do agree that die is a seperate IC though?

 

[Quaz51]

this Wafer is a 10S process and the 10S (90nm),11S (65nm) ,12S (45nm) process (SOI,lowK) developed by STI for the Cell is not a eDRAM process, i think
the eDRAM+logic process is developed by Sony and Toshiba (for the GPU probably) and named CMOS4 (90nm> PSP chip and EE+GS chip), CMOS5 (65nm > PS3 GPU?), CMOS6 (45nm, PS3 GPU evolution) and is not SOI

Good point...do agree that die is a seperate IC though?

i don't know, usually an IC is nearly square, this IC is very elongate...

 

[version]

if not eDRAM then possible about 4 MB cache?
i dont know....

 

[j^aws]

I can't find GS wafer but this is EE+GS (86 mm2)...there are uniform banks of eDRAM on the die...

 

[j^aws]

this Wafer is a 10S process and the 10S (90nm),11S (65nm) ,12S (45nm) process (SOI,lowK) developed by STI for the Cell is not a eDRAM process, i think
the eDRAM+logic process is developed by Sony and Toshiba (for the GPU probably) and named CMOS4 (90nm> PSP chip and EE+GS chip), CMOS5 (65nm > PS3 GPU?), CMOS6 (45nm, PS3 GPU evolution) and is not SOI

Good point...do agree that die is a seperate IC though?

i don't know, usually an IC is nearly square, this IC is very elongate...

It still has one side with 3/4 pools of solder pads...2nd pad from top is as wide as FlexIO/ XIO...?

 

[Panajev2001a]

this Wafer is a 10S process and the 10S (90nm),11S (65nm) ,12S (45nm) process (SOI,lowK) developed by STI for the Cell is not a eDRAM process, i think
the eDRAM+logic process is developed by Sony and Toshiba (for the GPU probably) and named CMOS4 (90nm> PSP chip and EE+GS chip), CMOS5 (65nm > PS3 GPU?), CMOS6 (45nm, PS3 GPU evolution) and is not SOI

Good point...do agree that die is a seperate IC though?

Wrong, CMOS5 has been intended to use SOI and e-DRAM in a mixed loading process (both SOI, for the logic, and bulk-CMOS for the e-DRAM although they might go bulk-CMOS only if they have major problems with e-DRAM integration) while for the 45 nm node Toshiba has made a quite nice breakthrough with capacitor-less e-DRAM using SOI's properties to store the charge: this is likely what will end up in CMOS6.

 

[j^aws]

this Wafer is a 10S process and the 10S (90nm),11S (65nm) ,12S (45nm) process (SOI,lowK) developed by STI for the Cell is not a eDRAM process, i think
the eDRAM+logic process is developed by Sony and Toshiba (for the GPU probably) and named CMOS4 (90nm> PSP chip and EE+GS chip), CMOS5 (65nm > PS3 GPU?), CMOS6 (45nm, PS3 GPU evolution) and is not SOI

Good point...do agree that die is a seperate IC though?

Wrong, CMOS5 has been intended to use SOI and e-DRAM in a mixed loading process (both SOI, for the logic, and bulk-CMOS for the e-DRAM although they might go bulk-CMOS only if they have major problems with e-DRAM integration) while for the 45 nm node Toshiba has made a quite nice breakthrough with capacitor-less e-DRAM using SOI's properties to store the charge: this is likely what will end up in CMOS6.

What's this...a drive-thru post!

I think it was a recent Japanese press claiming/ speculating that the GPU would be bulk-CMOS because of likely eDRAM and CELL would be SOI. Just to clarify are ALL STI fabs capable of mixed-loading? If the above wafer is from IBM's Fishkill, can it support eDRAM? If so, could that mystery IC above be the IOP with EE+GS? If not, is it an IC at least (GPU?) because of those 3/4 solder pad areas on one edge? Questions, I know, but I'm frigging curious!

 

[rendezvous]

It still has one side with 3/4 pools of solder pads...2nd pad from top is as wide as FlexIO/ XIO...?

From the original picture one can see that there is solder balls on the whole upper part if the die that you have pointed out with arrows. It's easy to be fooled by the reflections in the underlying structures and JPEG compression artefacts.
The rest of the chip olso seems to be covered by solder balls, there is however one area of the chip where i can't see any. I suspect that those contacts however are for power distribution.

 

[j^aws]

It still has one side with 3/4 pools of solder pads...2nd pad from top is as wide as FlexIO/ XIO...?

From the original picture one can see that there is solder balls on the whole upper part if the die that you have pointed out with arrows. It's easy to be fooled by the reflections in the underlying structures and JPEG compression artefacts.
The rest of the chip olso seems to be covered by solder balls, there is however one area of the chip where i can't see any. I suspect that those contacts however are for power distribution.

Sorry, I must be missing something but I could only see the top, long edge with the solder pads...could you please point the rest out?

EDIT: I take it you mean the all the 'pimples' but I can't see the 'blank' area?

 

[V3]

It could be the high performance switch to combine 4+ cells.

 

[j^aws]

It could be the high performance switch to combine 4+ cells.

Could be but the switch is needed for a 4 CELL setup and on the wafer you have 2 CELLs per 'other' IC...?

 

[V3]

Could be but the switch is needed for a 4 CELL setup and on the wafer you have 2 CELLs per 'other' IC...?

You don't get 100% yield, so its reasonable they do something like that.

 

[j^aws]

Could be but the switch is needed for a 4 CELL setup and on the wafer you have 2 CELLs per 'other' IC...?

You don't get 100% yield, so its reasonable they do something like that.

Okay...good shout but if you look at the top edge, you seem to see a set of interfaces not catering for enough FlexIO connections...?

 

[V3]

Okay...good shout but if you look at the top edge, you seem to see a set of interfaces not catering for enough FlexIO connections...?

Well with that quality picture and angle like that, even zoom in like that, its hard to make out the kind of detail you're asking for.

 

[j^aws]

Okay...good shout but if you look at the top edge, you seem to see a set of interfaces not catering for enough FlexIO connections...?

Well with that quality picture and angle like that, even zoom in like that, its hard to make out the kind of detail you're asking for.

I know...it's all we have.

But it seems the top edge has 1 FlexIO interface and 3 other, much smaller interfaces, which leads me to believe it's the IOP and not a GPU...?

 

[rendezvous]

I should have made a picture with my first post, but i was too lazy. Sorry about that.

I can find any solder bumps in the area marked with red on any of the dies in the picture. It's possibly compression artefacts so i don't think it's anything to worry about.
You can see that the assumed interface actually is one are that stretches the complete length of the die in the area marked with green.
The area marked with blue also seems to have an higher densisty of solder bumps.

It is a pretty big thing we are speculating on. It's larger than the cell dies.

 

[Panajev2001a]

this Wafer is a 10S process and the 10S (90nm),11S (65nm) ,12S (45nm) process (SOI,lowK) developed by STI for the Cell is not a eDRAM process, i think
the eDRAM+logic process is developed by Sony and Toshiba (for the GPU probably) and named CMOS4 (90nm> PSP chip and EE+GS chip), CMOS5 (65nm > PS3 GPU?), CMOS6 (45nm, PS3 GPU evolution) and is not SOI

Good point...do agree that die is a seperate IC though?

Wrong, CMOS5 has been intended to use SOI and e-DRAM in a mixed loading process (both SOI, for the logic, and bulk-CMOS for the e-DRAM although they might go bulk-CMOS only if they have major problems with e-DRAM integration) while for the 45 nm node Toshiba has made a quite nice breakthrough with capacitor-less e-DRAM using SOI's properties to store the charge: this is likely what will end up in CMOS6.

What's this...a drive-thru post!

I think it was a recent Japanese press claiming/ speculating that the GPU would be bulk-CMOS because of likely eDRAM and CELL would be SOI. Just to clarify are ALL STI fabs capable of mixed-loading? If the above wafer is from IBM's Fishkill, can it support eDRAM? If so, could that mystery IC above be the IOP with EE+GS? If not, is it an IC at least (GPU?) because of those 3/4 solder pad areas on one edge? Questions, I know, but I'm frigging curious!

There are some problems regarding mixed-loading apparently: likely the reason why the pans of lots of e-DRAM on the CPU were abandoned and the GPU is rumored to be realized in bulk-CMOS even in the 65 nm node.

He is right that CMOS4 is not SOI, CMOS5 is now looking to not have taken the mixed-loading idea, but once they have perfected their e-DRAM on SOI (capacitor-less e-DRAM) for their 45 nm node there is one less step between making the GPU wholly with an SOI manufacturing process as the final specs of CMOS6 has not been completed yet, they have not finished the libraries for the process yet IIRC.

 

[j^aws]

I should have made a picture with my first post, but i was too lazy. Sorry about that.

I can find any solder bumps in the area marked with red on any of the dies in the picture. It's possibly compression artefacts so i don't think it's anything to worry about.
You can see that the assumed interface actually is one are that stretches the complete length of the die in the area marked with green.
The area marked with blue also seems to have an higher densisty of solder bumps.

It is a pretty big thing we are speculating on. It's larger than the cell dies.

I've estimated that die ~ 250 mm2 which is very large. The CELL die is ~ 221 mm2

That square blue block you've highlighted seems isolated from the rest of the die. It's ~ 55 mm2. That could be around 4MB of cache or 32MB eDRAM. However, this wafers from IBM and wouldn't have any eDRAM process.

If it's the IOP, it wouldn't then have the EE+GS (86mm2) because of eDRAM needed (4MB) and would be freakin huge for an IOP anyway...?

If it's a GPU, then it wouldn't have eDRAM also but could have 4MB cache instead in that blue square highlighted block...?

I can't think of any other large IC that would go with CELL at 90nm except that 4-way switch but it doesn't seem to have enough interfaces to connect to 4 CELLs...?

I see 4 interfaces, 1 large FlexIO size interface and 3 much smaller ones...?

Oh well...it would seem 2 CELLs would be needed for 1 of those IC's...

 

[rendezvous]

Are you counting the sizes of the interfaces in area or solder bumps?
The solder bump dencities seems to be much higher on the cell chips.
Counting the soulder bumps in the area of the FlexIO interfaces gives about 500 bumps.

And would a 4-way switch really need to be _that_ large?

I guess we can keep on guessing for quite a while becouse i don't think well get to know what that is for some time.

 

[j^aws]

Are you counting the sizes of the interfaces in area or solder bumps?
The solder bump dencities seems to be much higher on the cell chips.
Counting the soulder bumps in the area of the FlexIO interfaces gives about 500 bumps.
...

Now that you mention it, I was eyeballing the 4 areas and not the density of solder bumps on the IC. The largest area is similar to size to the FlexIO. But the FlexIO does have ~ 500 bumps and the other IC ~ 200 bumps.

This much lower density actually leans me more towards an IOP more than the GPU (which was announced to be manufactured in Sony-Tosh fabs and not IBMs).

The IOP would need far less bandwidth to the CPU than a CPU<=>GPU connection bandwidth by the FlexIO. The IC has 4 I/O areas (4 bump areas) which would fit inline for an IOP. A GPU would have a FlexIO, possibly XIO and video out but what would it need 4 for?

But the lack of eDRAM on wafer would mean no EE+GS core on the IOP...but that could itself be a seperate off-chip addition. However, that's still huge for an IOP!

IOP= Media core/sound core/network-wifi core/ IO core and large lump of cache...?

...
And would a 4-way switch really need to be _that_ large?...

Not sure....they would need to connect 4 CELLs via FlexIO. Each FlexIO is 96bit (12*8 bit lanes). They'd prolly need to connect these 12 lanes from each CELL to 3 other CELLs FlexIO. I can't see how that would come anywhere near a 250 mm2 IC switch on 90nm!

Also they only need a switch for 4 or more CELLs and the wafer has a 2:1 ratio to the IC. The IC also has 4 non-homogeneous interface areas which wouldn't fit with 4 homogeneous CELL FlexIO interfaces.

...
I guess we can keep on guessing for quite a while becouse i don't think well get to know what that is for some time.

Yeah looks like it! ...But at least this wafer also has this other, mystery IC with the CELLs directly from the IBM fab...